clkscan3.map.eqn

采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1：当按下启动计时按钮时

--S61L21 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~63
--operation mode is arithmetic

S61L21 = CARRY(S61L31);


--S51L8 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~53
--operation mode is arithmetic

S51L8 = CARRY(!M4L81 & !M4L71 & !S51L21);


--S5L4 is clkscan:inst7|lpm_divide:div_rtl_3|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~48
--operation mode is arithmetic

S5L4 = CARRY(!M2L5 & !M2L6 & !S5L8);


--S9L6 is clkscan:inst7|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~48
--operation mode is arithmetic

S9L6 = CARRY(!M3L5 & !M3L6 & !S9L01);


--S81L4 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~48
--operation mode is arithmetic

S81L4 = CARRY(!M5L21 & !M5L11 & !S81L8);


--M5L31 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[26]~23
--operation mode is normal

M5L31 = E1_hour[3] & (!S81L2);


--M5L41 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[26]~28
--operation mode is normal

M5L41 = S81L2 & (!E1_hour[3]);


--S91L8 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~58
--operation mode is arithmetic

S91L8 = CARRY(S91L11);


--S41L6 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~48
--operation mode is arithmetic

S41L6 = CARRY(!M4L21 & !M4L11 & !S41L01);


--M4L31 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[26]~23
--operation mode is normal

M4L31 = E1_sec[3] & (!S41L4);


--M4L41 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[26]~28
--operation mode is normal

M4L41 = S41L4 & (!S41_add_sub_cella[1]);


--S51L01 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~58
--operation mode is arithmetic

S51L01 = CARRY(S51L31);


--S22L4 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~48
--operation mode is arithmetic

S22L4 = CARRY(!M6L21 & !M6L11 & !S22L8);


--M6L31 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[26]~23
--operation mode is normal

M6L31 = E1_min[3] & (!S22L2);


--M6L41 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[26]~28
--operation mode is normal

M6L41 = S22L2 & (!E1_min[3]);


--S32L8 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~58
--operation mode is arithmetic

S32L8 = CARRY(S32L11);


--S1L4 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~48
--operation mode is arithmetic

S1L4 = CARRY(!M1L5 & !M1L6 & !S1L8);


--S3L7 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~51
--operation mode is arithmetic

S3L7_carry_eqn = S3L01;
S3L7 = S3L7_carry_eqn $ (!M1L61 & !M1L51);

--S3L8 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~53
--operation mode is arithmetic

S3L8 = CARRY(!S3L01 & (M1L61 # M1L51));


--E1_hour[4] is timer:inst6|hour[4]
--operation mode is arithmetic

E1_hour[4]_lut_out = E1L72;
E1_hour[4] = DFFEAS(E1_hour[4]_lut_out, E1_h_clk, D2_signal, , , , , !E1L25, );

--S1L1 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]~COUT
--operation mode is arithmetic

S1L1 = CARRY(E1_hour[4]);


--M1L61 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[27]~525
--operation mode is normal

M1L61 = !S2L4 & (S1L2 $ E1_hour[4]);


--S2L7 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~51
--operation mode is arithmetic

S2L7_carry_eqn = S2L21;
S2L7 = S2L7_carry_eqn $ (!M1L7 & !M1L8);

--S2L8 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~53
--operation mode is arithmetic

S2L8 = CARRY(!M1L7 & !M1L8 & !S2L21);


--M1L51 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[27]~27
--operation mode is normal

M1L51 = S2L4 & S2L7;


--M1L22 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[33]~526
--operation mode is normal

M1L22 = S3L4 & S3L7 # !S3L4 & (M1L61 # M1L51);


--S4L5 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~80
--operation mode is arithmetic

S4L5 = CARRY(!S4L7 & (M1L12 # M1L02));


--B1_count[21] is clkdiv:inst|count[21]
--operation mode is normal

B1_count[21]_lut_out = B1L1;
B1_count[21] = DFFEAS(B1_count[21]_lut_out, clk, VCC, , , , , , );


--B1_count[22] is clkdiv:inst|count[22]
--operation mode is normal

B1_count[22]_lut_out = B1L3 & B1L17;
B1_count[22] = DFFEAS(B1_count[22]_lut_out, clk, VCC, , , , , , );


--B1L27 is clkdiv:inst|reduce_nor~175
--operation mode is normal

B1L27 = B1_count[21] # !B1_count[22];


--B1_count[20] is clkdiv:inst|count[20]
--operation mode is normal

B1_count[20]_lut_out = B1L4;
B1_count[20] = DFFEAS(B1_count[20]_lut_out, clk, VCC, , , , , , );


--B1_count[17] is clkdiv:inst|count[17]
--operation mode is normal

B1_count[17]_lut_out = B1L6;
B1_count[17] = DFFEAS(B1_count[17]_lut_out, clk, VCC, , , , , , );


--B1_count[16] is clkdiv:inst|count[16]
--operation mode is normal

B1_count[16]_lut_out = B1L8;
B1_count[16] = DFFEAS(B1_count[16]_lut_out, clk, VCC, , , , , , );


--B1_count[15] is clkdiv:inst|count[15]
--operation mode is normal

B1_count[15]_lut_out = B1L01;
B1_count[15] = DFFEAS(B1_count[15]_lut_out, clk, VCC, , , , , , );


--B1_count[18] is clkdiv:inst|count[18]
--operation mode is normal

B1_count[18]_lut_out = B1L21 & B1L17;
B1_count[18] = DFFEAS(B1_count[18]_lut_out, clk, VCC, , , , , , );


--B1L37 is clkdiv:inst|reduce_nor~176
--operation mode is normal

B1L37 = B1_count[17] # B1_count[16] # B1_count[15] # !B1_count[18];


--B1_count[19] is clkdiv:inst|count[19]
--operation mode is normal

B1_count[19]_lut_out = B1L41 & B1L17;
B1_count[19] = DFFEAS(B1_count[19]_lut_out, clk, VCC, , , , , , );


--B1L47 is clkdiv:inst|reduce_nor~177
--operation mode is normal

B1L47 = B1L27 # B1_count[20] # B1L37 # !B1_count[19];


--B1_count[13] is clkdiv:inst|count[13]
--operation mode is normal

B1_count[13]_lut_out = B1L61;
B1_count[13] = DFFEAS(B1_count[13]_lut_out, clk, VCC, , , , , , );


--B1_count[12] is clkdiv:inst|count[12]
--operation mode is normal

B1_count[12]_lut_out = B1L81;
B1_count[12] = DFFEAS(B1_count[12]_lut_out, clk, VCC, , , , , , );


--B1_count[14] is clkdiv:inst|count[14]
--operation mode is normal

B1_count[14]_lut_out = B1L02 & B1L17;
B1_count[14] = DFFEAS(B1_count[14]_lut_out, clk, VCC, , , , , , );


--B1_count[11] is clkdiv:inst|count[11]
--operation mode is normal

B1_count[11]_lut_out = B1L22 & B1L17;
B1_count[11] = DFFEAS(B1_count[11]_lut_out, clk, VCC, , , , , , );


--B1L57 is clkdiv:inst|reduce_nor~178
--operation mode is normal

B1L57 = B1_count[13] # B1_count[12] # !B1_count[11] # !B1_count[14];


--B1_count[10] is clkdiv:inst|count[10]
--operation mode is normal

B1_count[10]_lut_out = B1L42;
B1_count[10] = DFFEAS(B1_count[10]_lut_out, clk, VCC, , , , , , );


--B1_count[7] is clkdiv:inst|count[7]
--operation mode is normal

B1_count[7]_lut_out = B1L62;
B1_count[7] = DFFEAS(B1_count[7]_lut_out, clk, VCC, , , , , , );


--B1_count[9] is clkdiv:inst|count[9]
--operation mode is normal

B1_count[9]_lut_out = B1L82 & B1L17;
B1_count[9] = DFFEAS(B1_count[9]_lut_out, clk, VCC, , , , , , );


--B1_count[8] is clkdiv:inst|count[8]
--operation mode is normal

B1_count[8]_lut_out = B1L03 & B1L17;
B1_count[8] = DFFEAS(B1_count[8]_lut_out, clk, VCC, , , , , , );


--B1L67 is clkdiv:inst|reduce_nor~179
--operation mode is normal

B1L67 = B1_count[10] # B1_count[7] # !B1_count[8] # !B1_count[9];


--B1_count[5] is clkdiv:inst|count[5]
--operation mode is normal

B1_count[5]_lut_out = B1L23;
B1_count[5] = DFFEAS(B1_count[5]_lut_out, clk, VCC, , , , , , );


--B1_count[4] is clkdiv:inst|count[4]
--operation mode is normal

B1_count[4]_lut_out = B1L43;
B1_count[4] = DFFEAS(B1_count[4]_lut_out, clk, VCC, , , , , , );


--B1_count[3] is clkdiv:inst|count[3]
--operation mode is normal

B1_count[3]_lut_out = B1L63;
B1_count[3] = DFFEAS(B1_count[3]_lut_out, clk, VCC, , , , , , );


--B1_count[6] is clkdiv:inst|count[6]
--operation mode is normal

B1_count[6]_lut_out = B1L83 & B1L17;
B1_count[6] = DFFEAS(B1_count[6]_lut_out, clk, VCC, , , , , , );


--B1L77 is clkdiv:inst|reduce_nor~180
--operation mode is normal

B1L77 = B1_count[5] # B1_count[4] # B1_count[3] # !B1_count[6];


--B1_count[2] is clkdiv:inst|count[2]
--operation mode is normal

B1_count[2]_lut_out = B1L04;
B1_count[2] = DFFEAS(B1_count[2]_lut_out, clk, VCC, , , , , , );


--B1_count[1] is clkdiv:inst|count[1]
--operation mode is normal

B1_count[1]_lut_out = B1L24;
B1_count[1] = DFFEAS(B1_count[1]_lut_out, clk, VCC, , , , , , );


--B1_count[0] is clkdiv:inst|count[0]
--operation mode is normal

B1_count[0]_lut_out = B1L44 & B1L17;
B1_count[0] = DFFEAS(B1_count[0]_lut_out, clk, VCC, , , , , , );


--B1L87 is clkdiv:inst|reduce_nor~181
--operation mode is normal

B1L87 = B1L77 # B1_count[2] # B1_count[1] # B1_count[0];


--B1L17 is clkdiv:inst|reduce_nor~0
--operation mode is normal

B1L17 = B1L47 # B1L57 # B1L67 # B1L87;


--D1_signal is button:inst5|signal
--operation mode is normal

D1_signal_lut_out = !D1L13 & !D1L51 & !D1L71 & !D1L02;
D1_signal = DFFEAS(D1_signal_lut_out, C1_clkout, VCC, , , , , , );


--S11L7 is clkscan:inst7|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~51
--operation mode is arithmetic

S11L7_carry_eqn = S11L01;
S11L7 = S11L7_carry_eqn $ (!M3L61 & !M3L51);

--S11L8 is clkscan:inst7|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~53
--operation mode is arithmetic

S11L8 = CARRY(!S11L01 & (M3L61 # M3L51));


--S9_add_sub_cella[1] is clkscan:inst7|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]
--operation mode is arithmetic

S9_add_sub_cella[1] = E1_sec[4];

--S9L3 is clkscan:inst7|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]~COUT
--operation mode is arithmetic

S9L3 = CARRY(E1_sec[4]);


--M3L61 is clkscan:inst7|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[27]~525
--operation mode is normal

M3L61 = !S01L4 & (S9L4 & (!S9_add_sub_cella[1]) # !S9L4 & E1_sec[4]);


--S01L7 is clkscan:inst7|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~51
--operation mode is arithmetic

S01L7_carry_eqn = S01L21;
S01L7 = S01L7_carry_eqn $ (!M3L7 & !M3L8);

--S01L8 is clkscan:inst7|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~53
--operation mode is arithmetic

S01L8 = CARRY(!M3L7 & !M3L8 & !S01L21);


--M3L51 is clkscan:inst7|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[27]~27
--operation mode is normal

M3L51 = S01L4 & S01L7;


--M3L22 is clkscan:inst7|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[33]~526
--operation mode is normal

M3L22 = S11L4 & S11L7 # !S11L4 & (M3L61 # M3L51);