clkscan3.map.eqn

采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1：当按下启动计时按钮时

--S61L6 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~48
--operation mode is arithmetic

S61L6 = CARRY(!M4L91 & !M4L02 & !S61L21);


--S51L4 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~41
--operation mode is normal

S51L4_carry_eqn = S51L8;
S51L4 = !S51L4_carry_eqn;


--S51_add_sub_cella[1] is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[1]
--operation mode is arithmetic

S51_add_sub_cella[1] = E1_sec[2];

--S51L3 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[1]~COUT
--operation mode is arithmetic

S51L3 = CARRY(E1_sec[2]);


--M4L02 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[31]~18
--operation mode is normal

M4L02 = S51L4 & (!S51_add_sub_cella[1]);


--E1_sec[2] is timer:inst6|sec[2]
--operation mode is arithmetic

E1_sec[2]_carry_eqn = E1L36;
E1_sec[2]_lut_out = E1_sec[2] $ (!E1_sec[2]_carry_eqn);
E1_sec[2] = DFFEAS(E1_sec[2]_lut_out, B1_clkout, D2_signal, , , , , E1L57, );

--E1L56 is timer:inst6|sec[2]~113
--operation mode is arithmetic

E1L56 = CARRY(E1_sec[2] & (!E1L36));


--M4L91 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[31]~13
--operation mode is normal

M4L91 = E1_sec[2] & (!S51L4);


--F1L21 is clkscan:inst7|Select~1309
--operation mode is normal

F1L21 = S61L4 & S61L5 # !S61L4 & (M4L02 # M4L91);


--F1L31 is clkscan:inst7|Select~1310
--operation mode is normal

F1L31 = F1L11 # F1_scan_en[8] & F1L21;


--F1L41 is clkscan:inst7|Select~1311
--operation mode is normal

F1L41 = F1L31 # F1L01 & (S91L2 $ E1_hour[2]);


--S5L2 is clkscan:inst7|lpm_divide:div_rtl_3|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~41
--operation mode is normal

S5L2_carry_eqn = S5L4;
S5L2 = !S5L2_carry_eqn;


--S9L4 is clkscan:inst7|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~41
--operation mode is normal

S9L4_carry_eqn = S9L6;
S9L4 = !S9L4_carry_eqn;


--F1L51 is clkscan:inst7|Select~1313
--operation mode is normal

F1L51 = S5L2 & (F1_scan_en[4] # S9L4 & !F1_scan_en[1]) # !S5L2 & (S9L4 & !F1_scan_en[1]);


--S81L2 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~41
--operation mode is normal

S81L2_carry_eqn = S81L4;
S81L2 = !S81L2_carry_eqn;


--E1_hour[3] is timer:inst6|hour[3]
--operation mode is arithmetic

E1_hour[3]_lut_out = E1L25;
E1_hour[3] = DFFEAS(E1_hour[3]_lut_out, E1_h_clk, D2_signal, , , , , !E1L81, );

--S81L1 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[1]~COUT
--operation mode is arithmetic

S81L1 = CARRY(E1_hour[3]);


--M5L22 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[32]~609
--operation mode is normal

M5L22 = !S91L2 & (S81L2 $ E1_hour[3]);


--S91L3 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~46
--operation mode is arithmetic

S91L3_carry_eqn = S91L8;
S91L3 = S91L3_carry_eqn $ (!M5L31 & !M5L41);

--S91L4 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~48
--operation mode is arithmetic

S91L4 = CARRY(!M5L31 & !M5L41 & !S91L8);


--M5L12 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[32]~17
--operation mode is normal

M5L12 = S91L2 & S91L3;


--F1L61 is clkscan:inst7|Select~1314
--operation mode is normal

F1L61 = F1L51 # F1L01 & (M5L22 # M5L12);


--E1_sec[3] is timer:inst6|sec[3]
--operation mode is arithmetic

E1_sec[3]_carry_eqn = E1L56;
E1_sec[3]_lut_out = E1_sec[3] $ (E1_sec[3]_carry_eqn);
E1_sec[3] = DFFEAS(E1_sec[3]_lut_out, B1_clkout, D2_signal, , , , , E1L57, );

--E1L76 is timer:inst6|sec[3]~117
--operation mode is arithmetic

E1L76 = CARRY(!E1L56 # !E1_sec[3]);


--S41L4 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~41
--operation mode is normal

S41L4_carry_eqn = S41L6;
S41L4 = !S41L4_carry_eqn;


--S41_add_sub_cella[1] is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[1]
--operation mode is arithmetic

S41_add_sub_cella[1] = E1_sec[3];

--S41L3 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[1]~COUT
--operation mode is arithmetic

S41L3 = CARRY(E1_sec[3]);


--M4L22 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[32]~609
--operation mode is normal

M4L22 = !S51L4 & (S41L4 & (!S41_add_sub_cella[1]) # !S41L4 & E1_sec[3]);


--S51L5 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~46
--operation mode is arithmetic

S51L5_carry_eqn = S51L01;
S51L5 = S51L5_carry_eqn $ (!M4L31 & !M4L41);

--S51L6 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~48
--operation mode is arithmetic

S51L6 = CARRY(!M4L31 & !M4L41 & !S51L01);


--M4L12 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[32]~17
--operation mode is normal

M4L12 = S51L4 & S51L5;


--F1L71 is clkscan:inst7|Select~1315
--operation mode is normal

F1L71 = F1_scan_en[8] & !S61L4 & (M4L22 # M4L12);


--S02L5 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~51
--operation mode is arithmetic

S02L5_carry_eqn = S02L4;
S02L5 = S02L5_carry_eqn $ (!M5L22 & !M5L12);

--S02L6 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~53
--operation mode is arithmetic

S02L6 = CARRY(!S02L4 & (M5L22 # M5L12));


--S22L2 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~41
--operation mode is normal

S22L2_carry_eqn = S22L4;
S22L2 = !S22L2_carry_eqn;


--E1_min[3] is timer:inst6|min[3]
--operation mode is arithmetic

E1_min[3]_lut_out = E1L02;
E1_min[3] = DFFEAS(E1_min[3]_lut_out, E1_min_clk, D2_signal, , , , , !E1L15, );

--S22L1 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[1]~COUT
--operation mode is arithmetic

S22L1 = CARRY(E1_min[3]);


--M6L22 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[32]~609
--operation mode is normal

M6L22 = !S32L2 & (S22L2 $ E1_min[3]);


--S32L3 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~46
--operation mode is arithmetic

S32L3_carry_eqn = S32L8;
S32L3 = S32L3_carry_eqn $ (!M6L31 & !M6L41);

--S32L4 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~48
--operation mode is arithmetic

S32L4 = CARRY(!M6L31 & !M6L41 & !S32L8);


--M6L12 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[32]~17
--operation mode is normal

M6L12 = S32L2 & S32L3;


--F1L81 is clkscan:inst7|Select~1316
--operation mode is normal

F1L81 = F1_scan_en[2] & !S42L2 & (M6L22 # M6L12);


--S61L7 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~51
--operation mode is arithmetic

S61L7_carry_eqn = S61L6;
S61L7 = S61L7_carry_eqn $ (!M4L22 & !M4L12);

--S61L8 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~53
--operation mode is arithmetic

S61L8 = CARRY(!S61L6 & (M4L22 # M4L12));


--F1L91 is clkscan:inst7|Select~1317
--operation mode is normal

F1L91 = F1L81 # S61L4 & S61L7 & F1_scan_en[8];


--S42L5 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~51
--operation mode is arithmetic

S42L5_carry_eqn = S42L4;
S42L5 = S42L5_carry_eqn $ (!M6L22 & !M6L12);

--S42L6 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~53
--operation mode is arithmetic

S42L6 = CARRY(!S42L4 & (M6L22 # M6L12));


--S1L2 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~41
--operation mode is normal

S1L2_carry_eqn = S1L4;
S1L2 = !S1L2_carry_eqn;


--F1L02 is clkscan:inst7|Select~1318
--operation mode is normal

F1L02 = S42L2 & F1_scan_en[2];


--F1L12 is clkscan:inst7|Select~1319
--operation mode is normal

F1L12 = S42L5 & (F1L02 # S1L2 & F1_scan_en[7]) # !S42L5 & S1L2 & F1_scan_en[7];


--S4L3 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~75
--operation mode is arithmetic

S4L3 = CARRY(M1L22 & !F1_scan_en[7] & !S4L5 # !M1L22 & (!S4L5 # !F1_scan_en[7]));


--B1_clkout is clkdiv:inst|clkout
--operation mode is normal

B1_clkout_lut_out = !B1L17;
B1_clkout = DFFEAS(B1_clkout_lut_out, clk, VCC, , , , , , );


--E1L35 is timer:inst6|reduce_nor~140
--operation mode is normal

E1L35 = E1_sec[0] & E1_sec[1] & E1_sec[3] & !E1_sec[2];


--E1_sec[5] is timer:inst6|sec[5]
--operation mode is arithmetic

E1_sec[5]_carry_eqn = E1L96;
E1_sec[5]_lut_out = E1_sec[5] $ (E1_sec[5]_carry_eqn);
E1_sec[5] = DFFEAS(E1_sec[5]_lut_out, B1_clkout, D2_signal, , , , , E1L57, );

--E1L17 is timer:inst6|sec[5]~121
--operation mode is arithmetic

E1L17 = CARRY(!E1L96 # !E1_sec[5]);


--E1_sec[4] is timer:inst6|sec[4]
--operation mode is arithmetic

E1_sec[4]_carry_eqn = E1L76;
E1_sec[4]_lut_out = E1_sec[4] $ (!E1_sec[4]_carry_eqn);
E1_sec[4] = DFFEAS(E1_sec[4]_lut_out, B1_clkout, D2_signal, , , , , E1L57, );

--E1L96 is timer:inst6|sec[4]~125
--operation mode is arithmetic

E1L96 = CARRY(E1_sec[4] & (!E1L76));


--E1_sec[7] is timer:inst6|sec[7]
--operation mode is normal

E1_sec[7]_carry_eqn = E1L37;
E1_sec[7]_lut_out = E1_sec[7] $ (E1_sec[7]_carry_eqn);
E1_sec[7] = DFFEAS(E1_sec[7]_lut_out, B1_clkout, D2_signal, , , , , E1L57, );


--E1_sec[6] is timer:inst6|sec[6]
--operation mode is arithmetic

E1_sec[6]_carry_eqn = E1L17;
E1_sec[6]_lut_out = E1_sec[6] $ (!E1_sec[6]_carry_eqn);
E1_sec[6] = DFFEAS(E1_sec[6]_lut_out, B1_clkout, D2_signal, , , , , E1L57, );

--E1L37 is timer:inst6|sec[6]~133
--operation mode is arithmetic

E1L37 = CARRY(E1_sec[6] & (!E1L17));


--E1L45 is timer:inst6|reduce_nor~141
--operation mode is normal

E1L45 = E1_sec[5] & E1_sec[4] & !E1_sec[7] & !E1_sec[6];


--E1_started is timer:inst6|started
--operation mode is normal

E1_started_lut_out = VCC;
E1_started = DFFEAS(E1_started_lut_out, !D1_signal, D2_signal, , , , , , );


--E1L57 is timer:inst6|sec[7]~136
--operation mode is normal

E1L57 = E1L35 & E1L45 # !E1_started;


--E1L1 is timer:inst6|add~379
--operation mode is arithmetic

E1L1 = !E1_min[0];

--E1L2 is timer:inst6|add~381
--operation mode is arithmetic

E1L2 = CARRY(E1_min[0]);


--E1_min_clk is timer:inst6|min_clk
--operation mode is normal

E1_min_clk_lut_out = E1_started & E1L35 & E1L45;
E1_min_clk = DFFEAS(E1_min_clk_lut_out, B1_clkout, D2_signal, , , , , , );


--S21L3 is clkscan:inst7|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~75
--operation mode is arithmetic

S21L3 = CARRY(M3L22 & F1_scan_en[1] & !S21L5 # !M3L22 & (F1_scan_en[1] # !S21L5));


--S8L3 is clkscan:inst7|lpm_divide:div_rtl_3|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~75
--operation mode is arithmetic

S8L3 = CARRY(M2L22 & !F1_scan_en[4] & !S8L5 # !M2L22 & (!S8L5 # !F1_scan_en[4]));


--E1L3 is timer:inst6|add~384
--operation mode is arithmetic

E1L3 = !E1_hour[0];

--E1L4 is timer:inst6|add~386
--operation mode is arithmetic

E1L4 = CARRY(E1_hour[0]);