clkscan3.map.eqn

采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1：当按下启动计时按钮时

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--F1_data[0] is clkscan:inst7|data[0]
--operation mode is normal

F1_data[0]_lut_out = S4L1 # F1L1 # F1L2;
F1_data[0] = DFFEAS(F1_data[0]_lut_out, !C1_clkout, D2_signal, , , , , , );


--F1_data[1] is clkscan:inst7|data[1]
--operation mode is normal

F1_data[1]_lut_out = F1L6 # F1_scan_en[2] & (S42L2 $ E1_min[1]);
F1_data[1] = DFFEAS(F1_data[1]_lut_out, !C1_clkout, D2_signal, , , , , , );


--F1_data[2] is clkscan:inst7|data[2]
--operation mode is normal

F1_data[2]_lut_out = F1L8 # F1L41 # F1_scan_en[2] & F1L9;
F1_data[2] = DFFEAS(F1_data[2]_lut_out, !C1_clkout, D2_signal, , , , , , );


--F1_data[3] is clkscan:inst7|data[3]
--operation mode is normal

F1_data[3]_lut_out = F1L61 # F1L22 # F1L91 # F1L12;
F1_data[3] = DFFEAS(F1_data[3]_lut_out, !C1_clkout, D2_signal, , , , , , );


--G1L4 is p7segment:inst8|out[6]~44
--operation mode is normal

G1L4 = F1_data[1] & !F1_data[3] & (!F1_data[2] # !F1_data[0]) # !F1_data[1] & (F1_data[2] $ F1_data[3]);


--G1L3 is p7segment:inst8|out[5]~45
--operation mode is normal

G1L3 = F1_data[0] & (F1_data[1] # F1_data[2] $ !F1_data[3]) # !F1_data[0] & (F1_data[2] & (F1_data[3]) # !F1_data[2] & F1_data[1]);


--G1L2 is p7segment:inst8|out[4]~46
--operation mode is normal

G1L2 = F1_data[0] # F1_data[1] & (F1_data[3]) # !F1_data[1] & F1_data[2];


--G1L1 is p7segment:inst8|out[3]~47
--operation mode is normal

G1L1 = F1_data[1] & (F1_data[3] # F1_data[0] & F1_data[2]) # !F1_data[1] & (F1_data[2] $ (F1_data[0] & !F1_data[3]));


--G1L5 is p7segment:inst8|reduce_or~47
--operation mode is normal

G1L5 = F1_data[2] & (F1_data[3]) # !F1_data[2] & F1_data[1] & (F1_data[3] # !F1_data[0]);


--G1L6 is p7segment:inst8|reduce_or~48
--operation mode is normal

G1L6 = F1_data[2] & (F1_data[3] # F1_data[0] $ F1_data[1]) # !F1_data[2] & (F1_data[1] & F1_data[3]);


--G1L7 is p7segment:inst8|reduce_or~49
--operation mode is normal

G1L7 = F1_data[1] & (F1_data[3]) # !F1_data[1] & (F1_data[2] $ (F1_data[0] & !F1_data[3]));


--F1_scan_en[8] is clkscan:inst7|scan_en[8]
--operation mode is normal

F1_scan_en[8]_lut_out = F1_scan_en[7];
F1_scan_en[8] = DFFEAS(F1_scan_en[8]_lut_out, !C1_clkout, D2_signal, , , , , , );


--F1_scan_en[7] is clkscan:inst7|scan_en[7]
--operation mode is normal

F1_scan_en[7]_lut_out = F1_scan_en[5];
F1_scan_en[7] = DFFEAS(F1_scan_en[7]_lut_out, !C1_clkout, D2_signal, , , , , , );


--F1_scan_en[5] is clkscan:inst7|scan_en[5]
--operation mode is normal

F1_scan_en[5]_lut_out = F1_scan_en[4];
F1_scan_en[5] = DFFEAS(F1_scan_en[5]_lut_out, !C1_clkout, D2_signal, , , , , , );


--F1_scan_en[4] is clkscan:inst7|scan_en[4]
--operation mode is normal

F1_scan_en[4]_lut_out = F1_scan_en[2];
F1_scan_en[4] = DFFEAS(F1_scan_en[4]_lut_out, !C1_clkout, D2_signal, , , , , , );


--F1_scan_en[2] is clkscan:inst7|scan_en[2]
--operation mode is normal

F1_scan_en[2]_lut_out = !F1_scan_en[1];
F1_scan_en[2] = DFFEAS(F1_scan_en[2]_lut_out, !C1_clkout, D2_signal, , , , , , );


--F1_scan_en[1] is clkscan:inst7|scan_en[1]
--operation mode is normal

F1_scan_en[1]_lut_out = !F1_scan_en[8];
F1_scan_en[1] = DFFEAS(F1_scan_en[1]_lut_out, !C1_clkout, D2_signal, , , , , , );


--S4L1 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~68
--operation mode is normal

S4L1_carry_eqn = S4L3;
S4L1 = !S4L1_carry_eqn;


--E1_sec[0] is timer:inst6|sec[0]
--operation mode is arithmetic

E1_sec[0]_lut_out = !E1_sec[0];
E1_sec[0] = DFFEAS(E1_sec[0]_lut_out, B1_clkout, D2_signal, , , , , E1L57, );

--E1L16 is timer:inst6|sec[0]~105
--operation mode is arithmetic

E1L16 = CARRY(E1_sec[0]);


--E1_min[0] is timer:inst6|min[0]
--operation mode is normal

E1_min[0]_lut_out = E1L1;
E1_min[0] = DFFEAS(E1_min[0]_lut_out, E1_min_clk, D2_signal, , , , , , );


--F1L1 is clkscan:inst7|Select~1296
--operation mode is normal

F1L1 = E1_sec[0] & (F1_scan_en[8] # F1_scan_en[2] & E1_min[0]) # !E1_sec[0] & F1_scan_en[2] & E1_min[0];


--S21L1 is clkscan:inst7|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~68
--operation mode is normal

S21L1_carry_eqn = S21L3;
S21L1 = !S21L1_carry_eqn;


--S8L1 is clkscan:inst7|lpm_divide:div_rtl_3|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~68
--operation mode is normal

S8L1_carry_eqn = S8L3;
S8L1 = !S8L1_carry_eqn;


--E1_hour[0] is timer:inst6|hour[0]
--operation mode is normal

E1_hour[0]_lut_out = E1L3;
E1_hour[0] = DFFEAS(E1_hour[0]_lut_out, E1_h_clk, D2_signal, , , , , , );


--F1L2 is clkscan:inst7|Select~1297
--operation mode is normal

F1L2 = S21L1 # S8L1 # F1_scan_en[5] & E1_hour[0];


--C1_clkout is clkdiv1ms:inst1|clkout
--operation mode is normal

C1_clkout_lut_out = !C1L15;
C1_clkout = DFFEAS(C1_clkout_lut_out, clk, VCC, , , , , , );


--D2_signal is button:inst9|signal
--operation mode is normal

D2_signal_lut_out = !D2L13 & !D2L51 & !D2L71 & !D2L02;
D2_signal = DFFEAS(D2_signal_lut_out, C1_clkout, VCC, , , , , , );


--S42L2 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~41
--operation mode is normal

S42L2_carry_eqn = S42L8;
S42L2 = !S42L2_carry_eqn;


--E1_min[1] is timer:inst6|min[1]
--operation mode is arithmetic

E1_min[1]_lut_out = E1L5;
E1_min[1] = DFFEAS(E1_min[1]_lut_out, E1_min_clk, D2_signal, , , , , , );

--S42L1 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[1]~COUT
--operation mode is arithmetic

S42L1 = CARRY(E1_min[1]);


--S3L4 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~41
--operation mode is normal

S3L4_carry_eqn = S3L6;
S3L4 = !S3L4_carry_eqn;


--E1_sec[1] is timer:inst6|sec[1]
--operation mode is arithmetic

E1_sec[1]_carry_eqn = E1L16;
E1_sec[1]_lut_out = E1_sec[1] $ (E1_sec[1]_carry_eqn);
E1_sec[1] = DFFEAS(E1_sec[1]_lut_out, B1_clkout, D2_signal, , , , , E1L57, );

--E1L36 is timer:inst6|sec[1]~109
--operation mode is arithmetic

E1L36 = CARRY(!E1L16 # !E1_sec[1]);


--S61L4 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~41
--operation mode is normal

S61L4_carry_eqn = S61L01;
S61L4 = !S61L4_carry_eqn;


--S61_add_sub_cella[1] is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[1]
--operation mode is arithmetic

S61_add_sub_cella[1] = E1_sec[1];

--S61L3 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[1]~COUT
--operation mode is arithmetic

S61L3 = CARRY(E1_sec[1]);


--F1L3 is clkscan:inst7|Select~1299
--operation mode is normal

F1L3 = F1_scan_en[8] & (S61L4 & (!S61_add_sub_cella[1]) # !S61L4 & E1_sec[1]);


--S02L2 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~41
--operation mode is normal

S02L2_carry_eqn = S02L8;
S02L2 = !S02L2_carry_eqn;


--E1_hour[1] is timer:inst6|hour[1]
--operation mode is arithmetic

E1_hour[1]_lut_out = E1L7;
E1_hour[1] = DFFEAS(E1_hour[1]_lut_out, E1_h_clk, D2_signal, , , , , , );

--S02L1 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[1]~COUT
--operation mode is arithmetic

S02L1 = CARRY(E1_hour[1]);


--S7L4 is clkscan:inst7|lpm_divide:div_rtl_3|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~41
--operation mode is normal

S7L4_carry_eqn = S7L6;
S7L4 = !S7L4_carry_eqn;


--S11L4 is clkscan:inst7|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~41
--operation mode is normal

S11L4_carry_eqn = S11L6;
S11L4 = !S11L4_carry_eqn;


--F1L4 is clkscan:inst7|Select~1300
--operation mode is normal

F1L4 = S7L4 & (F1_scan_en[4] # S11L4 & !F1_scan_en[1]) # !S7L4 & (S11L4 & !F1_scan_en[1]);


--F1L5 is clkscan:inst7|Select~1301
--operation mode is normal

F1L5 = F1L4 # F1_scan_en[5] & (S02L2 $ E1_hour[1]);


--F1L6 is clkscan:inst7|Select~1302
--operation mode is normal

F1L6 = F1L3 # F1L5 # S3L4 & F1_scan_en[7];


--S02L3 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~46
--operation mode is arithmetic

S02L3_carry_eqn = S02L01;
S02L3 = S02L3_carry_eqn $ (!M5L91 & !M5L02);

--S02L4 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~48
--operation mode is arithmetic

S02L4 = CARRY(!M5L91 & !M5L02 & !S02L01);


--S2L4 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~41
--operation mode is normal

S2L4_carry_eqn = S2L6;
S2L4 = !S2L4_carry_eqn;


--F1L7 is clkscan:inst7|Select~1304
--operation mode is normal

F1L7 = S02L2 & F1_scan_en[5];


--F1L8 is clkscan:inst7|Select~1305
--operation mode is normal

F1L8 = S02L3 & (F1L7 # S2L4 & F1_scan_en[7]) # !S02L3 & S2L4 & F1_scan_en[7];


--S32L2 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~41
--operation mode is normal

S32L2_carry_eqn = S32L6;
S32L2 = !S32L2_carry_eqn;


--E1_min[2] is timer:inst6|min[2]
--operation mode is arithmetic

E1_min[2]_lut_out = E1L15;
E1_min[2] = DFFEAS(E1_min[2]_lut_out, E1_min_clk, D2_signal, , , , , !E1L61, );

--S32L1 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[1]~COUT
--operation mode is arithmetic

S32L1 = CARRY(E1_min[2]);


--S42L3 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~46
--operation mode is arithmetic

S42L3_carry_eqn = S42L01;
S42L3 = S42L3_carry_eqn $ (!M6L91 & !M6L02);

--S42L4 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~48
--operation mode is arithmetic

S42L4 = CARRY(!M6L91 & !M6L02 & !S42L01);


--F1L9 is clkscan:inst7|Select~1306
--operation mode is normal

F1L9 = S42L2 & (S42L3) # !S42L2 & (S32L2 $ E1_min[2]);


--F1L01 is clkscan:inst7|Select~1307
--operation mode is normal

F1L01 = F1_scan_en[5] & (!S02L2);


--S91L2 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~41
--operation mode is normal

S91L2_carry_eqn = S91L6;
S91L2 = !S91L2_carry_eqn;


--E1_hour[2] is timer:inst6|hour[2]
--operation mode is arithmetic

E1_hour[2]_lut_out = E1L9;
E1_hour[2] = DFFEAS(E1_hour[2]_lut_out, E1_h_clk, D2_signal, , , , , , );

--S91L1 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[1]~COUT
--operation mode is arithmetic

S91L1 = CARRY(E1_hour[2]);


--S6L4 is clkscan:inst7|lpm_divide:div_rtl_3|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~41
--operation mode is normal

S6L4_carry_eqn = S6L6;
S6L4 = !S6L4_carry_eqn;


--S01L4 is clkscan:inst7|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~41
--operation mode is normal

S01L4_carry_eqn = S01L6;
S01L4 = !S01L4_carry_eqn;


--F1L11 is clkscan:inst7|Select~1308
--operation mode is normal

F1L11 = S6L4 & (F1_scan_en[4] # S01L4 & !F1_scan_en[1]) # !S6L4 & (S01L4 & !F1_scan_en[1]);


--S61L5 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~46
--operation mode is arithmetic

S61L5_carry_eqn = S61L21;
S61L5 = S61L5_carry_eqn $ (!M4L91 & !M4L02);