clkscan3.map.rpt

采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1：当按下启动计时按钮时

Info: Found 1 design units, including 1 entities, in source file clkscan3.bdf
    Info: Found entity 1: clkscan3
Info: Found 1 design units, including 1 entities, in source file clkscan3_test.bdf
    Info: Found entity 1: clkscan3_test
Info: Elaborating entity "clkscan3" for the top level hierarchy
Info: Elaborating entity "p7segment" for hierarchy "p7segment:inst8"
Info: Elaborating entity "clkscan" for hierarchy "clkscan:inst7"
Warning: Verilog HDL assignment warning at clkscan.v(23): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at clkscan.v(24): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clkscan.v(31): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at clkscan.v(32): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at clkscan.v(33): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at clkscan.v(34): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at clkscan.v(35): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at clkscan.v(36): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at clkscan.v(37): truncated value with size 32 to match size of target (8)
Info: Elaborating entity "clkdiv1ms" for hierarchy "clkdiv1ms:inst1"
Warning: Verilog HDL assignment warning at clkdiv1ms.v(10): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clkdiv1ms.v(12): truncated value with size 32 to match size of target (15)
Warning: Verilog HDL assignment warning at clkdiv1ms.v(14): truncated value with size 32 to match size of target (15)
Info: Elaborating entity "button" for hierarchy "button:inst9"
Warning: Verilog HDL assignment warning at button.v(11): truncated value with size 32 to match size of target (7)
Warning: Verilog HDL assignment warning at button.v(13): truncated value with size 32 to match size of target (7)
Info: Elaborating entity "timer" for hierarchy "timer:inst6"
Warning: Verilog HDL assignment warning at timer.v(11): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at timer.v(12): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at timer.v(17): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at timer.v(22): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at timer.v(23): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at timer.v(27): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at timer.v(28): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at timer.v(31): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at timer.v(38): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at timer.v(44): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at timer.v(45): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at timer.v(49): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at timer.v(50): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at timer.v(59): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at timer.v(65): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at timer.v(66): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at timer.v(70): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at timer.v(71): truncated value with size 32 to match size of target (8)
Info: Elaborating entity "clkdiv" for hierarchy "clkdiv:inst"
Warning: Verilog HDL assignment warning at clkdiv.v(10): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clkdiv.v(12): truncated value with size 32 to match size of target (23)
Warning: Verilog HDL assignment warning at clkdiv.v(14): truncated value with size 32 to match size of target (23)
Warning: Reduced register "clkscan:inst7|scan_en[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "clkscan:inst7|scan_en[3]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "button:inst5|enable~reg0" merged to single register "button:inst5|signal", power-up level changed
    Info: Duplicate register "button:inst9|enable~reg0" merged to single register "button:inst9|signal", power-up level changed
Info: State machine "|clkscan3|clkscan:inst7|state" contains 6 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|clkscan3|clkscan:inst7|state"
Info: Encoding result for state machine "|clkscan3|clkscan:inst7|state"
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit "clkscan:inst7|state.101"
        Info: Encoded state bit "clkscan:inst7|state.001"
        Info: Encoded state bit "clkscan:inst7|state.010"
        Info: Encoded state bit "clkscan:inst7|state.011"
        Info: Encoded state bit "clkscan:inst7|state.100"
        Info: Encoded state bit "clkscan:inst7|state.000"
    Info: State "|clkscan3|clkscan:inst7|state.000" uses code string "000000"
    Info: State "|clkscan3|clkscan:inst7|state.100" uses code string "000011"
    Info: State "|clkscan3|clkscan:inst7|state.011" uses code string "000101"
    Info: State "|clkscan3|clkscan:inst7|state.010" uses code string "001001"
    Info: State "|clkscan3|clkscan:inst7|state.001" uses code string "010001"
    Info: State "|clkscan3|clkscan:inst7|state.101" uses code string "100001"
Info: Duplicate registers merged to single register
    Info: Duplicate register "clkscan:inst7|state.101" merged to single register "clkscan:inst7|scan_en[8]"
    Info: Duplicate register "clkscan:inst7|state.100" merged to single register "clkscan:inst7|scan_en[7]"
    Info: Duplicate register "clkscan:inst7|state.011" merged to single register "clkscan:inst7|scan_en[5]"
    Info: Duplicate register "clkscan:inst7|state.010" merged to single register "clkscan:inst7|scan_en[4]"
    Info: Duplicate register "clkscan:inst7|state.001" merged to single register "clkscan:inst7|scan_en[2]"
    Info: Duplicate register "clkscan:inst7|state.000" merged to single register "clkscan:inst7|scan_en[1]", power-up level changed
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_divide.tdf
    Info: Found entity 1: lpm_divide
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_ndf.tdf
    Info: Found entity 1: lpm_divide_ndf
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_mhg.tdf
    Info: Found entity 1: sign_div_unsign_mhg
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_hld.tdf
    Info: Found entity 1: alt_u_div_hld
Info: Found 1 design units, including 1 entities, in source file db/add_sub_ke8.tdf
    Info: Found entity 1: add_sub_ke8
Info: Found 1 design units, including 1 entities, in source file db/add_sub_le8.tdf
    Info: Found entity 1: add_sub_le8
Info: Found 1 design units, including 1 entities, in source file db/add_sub_me8.tdf
    Info: Found entity 1: add_sub_me8
Info: Found 1 design units, including 1 entities, in source file db/add_sub_ne8.tdf
    Info: Found entity 1: add_sub_ne8
Info: Found 1 design units, including 1 entities, in source file db/add_sub_oe8.tdf
    Info: Found entity 1: add_sub_oe8
Info: Found 1 design units, including 1 entities, in source file db/add_sub_ma8.tdf
    Info: Found entity 1: add_sub_ma8
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_klf.tdf
    Info: Found entity 1: lpm_divide_klf
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "out[7]" stuck at GND
    Warning: Pin "scan_en[6]" stuck at GND
    Warning: Pin "scan_en[3]" stuck at GND
Info: Registers with preset signals will power-up high
Info: Implemented 579 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 16 output pins
    Info: Implemented 560 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 41 warnings
    Info: Processing ended: Mon Apr 14 21:13:50 2008
    Info: Elapsed time: 00:00:09