clkscan3.tan.talkback.xml

采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1：当按下启动计时按钮时

<!--
This XML file (created on Mon Apr 16 20:38:41 2007) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>5.0</ver>
<schema>quartus_version_5.0_build_148.xsd</schema><license>
	<host_id>50781c190dc3</host_id>
	<nic_id>50781c190dc3</nic_id>
	<cdrive_id>d4c45c75</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.0</version>
	<build>Build 148</build>
	<module>quartus_tan.exe</module>
	<edition>Full Version</edition>
	<compilation_end_time>Mon Apr 16 20:38:41 2007</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">2400</cpu_freq>
	</cpu>
	<ram units="MB">256</ram>
</machine>
<top_file>E:/clk_scan/clkscan3/clkscan3</top_file>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off clkscan3 -c clkscan3 --timing_analysis_only</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock &quot;clk&quot; with clock skew larger than data delay. See Compilation Report for details.</warning>
	<warning>Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew</warning>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings</info>
	<info>Info: Elapsed time: 00:00:02</info>
	<info>Info: Processing ended: Mon Apr 16 20:38:40 2007</info>
	<info>Info: th for register &quot;button:inst3|cnt[3]&quot; (data pin = &quot;start&quot;, clock pin = &quot;clk&quot;) is -3.949 ns</info>
	<info>Info: - Shortest pin to register delay is 11.685 ns</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>clk</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>NONE</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<based_on>NONE</based_on>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tsu</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>7.227 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>16.766 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case th</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>-3.949 ns</actual>
	</nonclk>
	<clk>
		<name>clk</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>15.02 MHz ( period = 66.560 ns )</actual>
	</clk>
</performance>
<compile_id>67F97043</compile_id>
</talkback>