📄 clkscan3.fit.talkback.xml
字号:
<name>out[0]</name>
<pin__>173</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>53</x_coordinate>
<y_coordinate>24</y_coordinate>
<cell_number>2</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>out[1]</name>
<pin__>169</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>53</x_coordinate>
<y_coordinate>23</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>out[2]</name>
<pin__>168</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>53</x_coordinate>
<y_coordinate>23</y_coordinate>
<cell_number>2</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>out[3]</name>
<pin__>167</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>53</x_coordinate>
<y_coordinate>22</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>out[4]</name>
<pin__>166</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>53</x_coordinate>
<y_coordinate>22</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>out[5]</name>
<pin__>165</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>53</x_coordinate>
<y_coordinate>22</y_coordinate>
<cell_number>2</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>out[6]</name>
<pin__>164</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>53</x_coordinate>
<y_coordinate>21</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>out[7]</name>
<pin__>163</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>53</x_coordinate>
<y_coordinate>21</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>scan_en[1]</name>
<pin__>139</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>53</x_coordinate>
<y_coordinate>6</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>scan_en[2]</name>
<pin__>140</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>53</x_coordinate>
<y_coordinate>7</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>scan_en[3]</name>
<pin__>141</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>53</x_coordinate>
<y_coordinate>7</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>scan_en[4]</name>
<pin__>158</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>53</x_coordinate>
<y_coordinate>19</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>scan_en[5]</name>
<pin__>159</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>53</x_coordinate>
<y_coordinate>20</y_coordinate>
<cell_number>2</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>scan_en[6]</name>
<pin__>160</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>53</x_coordinate>
<y_coordinate>20</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>scan_en[7]</name>
<pin__>161</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>53</x_coordinate>
<y_coordinate>20</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>scan_en[8]</name>
<pin__>162</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>53</x_coordinate>
<y_coordinate>21</y_coordinate>
<cell_number>2</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
</output_pins>
<compilation_summary>
<flow_status>Successful - Mon Apr 16 20:38:31 2007</flow_status>
<quartus_ii_version>5.0 Build 148 04/26/2005 SJ Web Edition</quartus_ii_version>
<revision_name>clkscan3</revision_name>
<top_level_entity_name>clkscan3</top_level_entity_name>
<family>Cyclone</family>
<device>EP1C12Q240C8</device>
<timing_models>Final</timing_models>
<met_timing_requirements>N/A</met_timing_requirements>
<total_logic_elements>531 / 12,060 ( 4 % )</total_logic_elements>
<total_pins>19 / 173 ( 10 % )</total_pins>
<total_virtual_pins>0</total_virtual_pins>
<total_memory_bits>0 / 239,616 ( 0 % )</total_memory_bits>
<total_plls>0 / 2 ( 0 % )</total_plls>
</compilation_summary>
<compile_id>550D90C3</compile_id>
<files>
<top>E:/clk_scan/clkscan3/clkscan3.bdf</top>
<extensions>
<ext ext_name="v">6</ext>
<ext ext_name="vwf">3</ext>
<ext ext_name="bdf">2</ext>
<ext ext_name="tdf">11</ext>
<ext ext_name="inc">3</ext>
<ext ext_name="lst">1</ext>
</extensions>
<sub_files>
<sub_file>E:/clk_scan/clkscan3/button.v</sub_file>
<sub_file>E:/clk_scan/clkscan3/clkdiv1ms.v</sub_file>
<sub_file>E:/clk_scan/clkscan3/clkdiv.v</sub_file>
<sub_file>E:/clk_scan/clkscan3/p7segment.v</sub_file>
<sub_file>E:/clk_scan/clkscan3/clkscan.v</sub_file>
<sub_file>E:/clk_scan/clkscan3/clkscan.vwf</sub_file>
<sub_file>E:/clk_scan/clkscan3/timer.v</sub_file>
<sub_file>E:/clk_scan/clkscan3/timer.vwf</sub_file>
<sub_file>E:/clk_scan/clkscan3/clkscan3.bdf</sub_file>
<sub_file>E:/clk_scan/clkscan3/clkscan3_test.bdf</sub_file>
<sub_file>E:/clk_scan/clkscan3/clkscan3.vwf</sub_file>
<sub_file>c:/altera/quartus50/libraries/megafunctions/lpm_divide.tdf</sub_file>
<sub_file>c:/altera/quartus50/libraries/megafunctions/abs_divider.inc</sub_file>
<sub_file>c:/altera/quartus50/libraries/megafunctions/sign_div_unsign.inc</sub_file>
<sub_file>c:/altera/quartus50/libraries/megafunctions/aglobal50.inc</sub_file>
<sub_file>c:/altera/quartus50/libraries/megafunctions/cbx.lst</sub_file>
<sub_file>E:/clk_scan/clkscan3/db/lpm_divide_ndf.tdf</sub_file>
<sub_file>E:/clk_scan/clkscan3/db/sign_div_unsign_mhg.tdf</sub_file>
<sub_file>E:/clk_scan/clkscan3/db/alt_u_div_hld.tdf</sub_file>
<sub_file>E:/clk_scan/clkscan3/db/add_sub_ke8.tdf</sub_file>
<sub_file>E:/clk_scan/clkscan3/db/add_sub_le8.tdf</sub_file>
<sub_file>E:/clk_scan/clkscan3/db/add_sub_me8.tdf</sub_file>
<sub_file>E:/clk_scan/clkscan3/db/add_sub_ne8.tdf</sub_file>
<sub_file>E:/clk_scan/clkscan3/db/add_sub_oe8.tdf</sub_file>
<sub_file>E:/clk_scan/clkscan3/db/add_sub_ma8.tdf</sub_file>
<sub_file>E:/clk_scan/clkscan3/db/lpm_divide_klf.tdf</sub_file>
</sub_files>
</files>
<architecture>
<family>Cyclone</family>
<auto_device>OFF</auto_device>
<device>EP1C12Q240C8</device>
</architecture>
<pkg_io>
<pin_std count="21">LVTTL</pin_std>
</pkg_io>
<research>
<le_sclr>14</le_sclr>
<le_aclr>95</le_aclr>
<le_aload>0</le_aload>
<le_sload>27</le_sload>
<le_inverta>0</le_inverta>
<le_carry_in>50</le_carry_in>
<le_ce>1</le_ce>
<le_clk>95</le_clk>
<le_ce_sload>0</le_ce_sload>
<pin_sclr>0</pin_sclr>
<pin_aclr>0</pin_aclr>
<pin_ce_in>0</pin_ce_in>
<pin_ce_out>0</pin_ce_out>
</research>
</talkback>
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -