at91c221.h

AT9260的BOOTLOADER,还有几个版本的,需要的我再放

#define AT91C_SDRC_TR   ((AT91_REG *) 	0xFF008004) // (SDRC) SDRAM Controller Refresh Timer Register
#define AT91C_SDRC_MR   ((AT91_REG *) 	0xFF008000) // (SDRC) SDRAM Controller Mode Register
#define AT91C_SDRC_CR   ((AT91_REG *) 	0xFF008008) // (SDRC) SDRAM Controller Configuration Register
#define AT91C_SDRC_ADDR ((AT91_REG *) 	0xFF008010) // (SDRC) SDRAM Base Address for SDCS
// ========== Register definition for PDC_US0 peripheral ========== 
#define AT91C_US0_TCR   ((AT91_REG *) 	0xFF01803C) // (PDC_US0) Transmit Counter Register
#define AT91C_US0_RCR   ((AT91_REG *) 	0xFF018034) // (PDC_US0) Receive Counter Register
#define AT91C_US0_RPR   ((AT91_REG *) 	0xFF018030) // (PDC_US0) Receive Pointer Register
#define AT91C_US0_TPR   ((AT91_REG *) 	0xFF018038) // (PDC_US0) Transmit Pointer Register
// ========== Register definition for US0 peripheral ========== 
#define AT91C_US0_IMR   ((AT91_REG *) 	0xFF018010) // (US0) Interrupt Mask Register
#define AT91C_US0_THR   ((AT91_REG *) 	0xFF01801C) // (US0) Transmitter Holding Register
#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFF018024) // (US0) Receiver Time-out Register
#define AT91C_US0_MS    ((AT91_REG *) 	0xFF018044) // (US0) Modem Status Register
#define AT91C_US0_CSR   ((AT91_REG *) 	0xFF018014) // (US0) Channel Status Register
#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFF018028) // (US0) Transmitter Time-guard Register
#define AT91C_US0_MC    ((AT91_REG *) 	0xFF018040) // (US0) Modem Control Register
#define AT91C_US0_MR    ((AT91_REG *) 	0xFF018004) // (US0) Mode Register
#define AT91C_US0_IDR   ((AT91_REG *) 	0xFF01800C) // (US0) Interrupt Disable Register
#define AT91C_US0_RHR   ((AT91_REG *) 	0xFF018018) // (US0) Receiver Holding Register
#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFF018020) // (US0) Baud Rate Generator Register
#define AT91C_US0_CR    ((AT91_REG *) 	0xFF018000) // (US0) Control Register
#define AT91C_US0_IER   ((AT91_REG *) 	0xFF018008) // (US0) Interrupt Enable Register
// ========== Register definition for PDC_US1 peripheral ========== 
#define AT91C_US1_RCR   ((AT91_REG *) 	0xFF01C034) // (PDC_US1) Receive Counter Register
#define AT91C_US1_TPR   ((AT91_REG *) 	0xFF01C038) // (PDC_US1) Transmit Pointer Register
#define AT91C_US1_TCR   ((AT91_REG *) 	0xFF01C03C) // (PDC_US1) Transmit Counter Register
#define AT91C_US1_RPR   ((AT91_REG *) 	0xFF01C030) // (PDC_US1) Receive Pointer Register
// ========== Register definition for US1 peripheral ========== 
#define AT91C_US1_CSR   ((AT91_REG *) 	0xFF01C014) // (US1) Channel Status Register
#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFF01C020) // (US1) Baud Rate Generator Register
#define AT91C_US1_IER   ((AT91_REG *) 	0xFF01C008) // (US1) Interrupt Enable Register
#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFF01C024) // (US1) Receiver Time-out Register
#define AT91C_US1_IDR   ((AT91_REG *) 	0xFF01C00C) // (US1) Interrupt Disable Register
#define AT91C_US1_CR    ((AT91_REG *) 	0xFF01C000) // (US1) Control Register
#define AT91C_US1_MS    ((AT91_REG *) 	0xFF01C044) // (US1) Modem Status Register
#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFF01C028) // (US1) Transmitter Time-guard Register
#define AT91C_US1_MR    ((AT91_REG *) 	0xFF01C004) // (US1) Mode Register
#define AT91C_US1_THR   ((AT91_REG *) 	0xFF01C01C) // (US1) Transmitter Holding Register
#define AT91C_US1_IMR   ((AT91_REG *) 	0xFF01C010) // (US1) Interrupt Mask Register
#define AT91C_US1_RHR   ((AT91_REG *) 	0xFF01C018) // (US1) Receiver Holding Register
#define AT91C_US1_MC    ((AT91_REG *) 	0xFF01C040) // (US1) Modem Control Register
// ========== Register definition for PDC_SPI peripheral ========== 
#define AT91C_SPI_TCR   ((AT91_REG *) 	0xFF02002C) // (PDC_SPI) Transmit Counter Register
#define AT91C_SPI_RPR   ((AT91_REG *) 	0xFF020020) // (PDC_SPI) Receive Pointer Register
#define AT91C_SPI_TPR   ((AT91_REG *) 	0xFF020028) // (PDC_SPI) Transmit Pointer Register
#define AT91C_SPI_RCR   ((AT91_REG *) 	0xFF020024) // (PDC_SPI) Receive Counter Register
// ========== Register definition for SPI peripheral ========== 
#define AT91C_SPI_IMR   ((AT91_REG *) 	0xFF02001C) // (SPI) Interrupt Mask Register
#define AT91C_SPI_TDR   ((AT91_REG *) 	0xFF02000C) // (SPI) Transmit Data Register
#define AT91C_SPI_MR    ((AT91_REG *) 	0xFF020004) // (SPI) Mode Register
#define AT91C_SPI_CR    ((AT91_REG *) 	0xFF020000) // (SPI) Control Register
#define AT91C_SPI_CSR   ((AT91_REG *) 	0xFF020030) // (SPI) Chip Select Register
#define AT91C_SPI_RDR   ((AT91_REG *) 	0xFF020008) // (SPI) Receive Data Register
#define AT91C_SPI_IDR   ((AT91_REG *) 	0xFF020018) // (SPI) Interrupt Disable Register
#define AT91C_SPI_SR    ((AT91_REG *) 	0xFF020010) // (SPI) Status Register
#define AT91C_SPI_IER   ((AT91_REG *) 	0xFF020014) // (SPI) Interrupt Enable Register
// ========== Register definition for TC2 peripheral ========== 
#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFF0140AC) // (TC2) Interrupt Mask Register
#define AT91C_TC2_RB    ((AT91_REG *) 	0xFF014098) // (TC2) Register B
#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFF014084) // (TC2) Channel Mode Register
#define AT91C_TC2_IER   ((AT91_REG *) 	0xFF0140A4) // (TC2) Interrupt Enable Register
#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFF014080) // (TC2) Channel Control Register
#define AT91C_TC2_SR    ((AT91_REG *) 	0xFF0140A0) // (TC2) Status Register
#define AT91C_TC2_RA    ((AT91_REG *) 	0xFF014094) // (TC2) Register A
#define AT91C_TC2_RC    ((AT91_REG *) 	0xFF01409C) // (TC2) Register C
#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFF0140A8) // (TC2) Interrupt Disable Register
#define AT91C_TC2_CVR   ((AT91_REG *) 	0xFF014090) // (TC2) Counter Value Register
// ========== Register definition for TC1 peripheral ========== 
#define AT91C_TC1_RB    ((AT91_REG *) 	0xFF014058) // (TC1) Register B
#define AT91C_TC1_RC    ((AT91_REG *) 	0xFF01405C) // (TC1) Register C
#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFF01406C) // (TC1) Interrupt Mask Register
#define AT91C_TC1_SR    ((AT91_REG *) 	0xFF014060) // (TC1) Status Register
#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFF014044) // (TC1) Channel Mode Register
#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFF014040) // (TC1) Channel Control Register
#define AT91C_TC1_IER   ((AT91_REG *) 	0xFF014064) // (TC1) Interrupt Enable Register
#define AT91C_TC1_CVR   ((AT91_REG *) 	0xFF014050) // (TC1) Counter Value Register
#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFF014068) // (TC1) Interrupt Disable Register
#define AT91C_TC1_RA    ((AT91_REG *) 	0xFF014054) // (TC1) Register A
// ========== Register definition for TC0 peripheral ========== 
#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFF01402C) // (TC0) Interrupt Mask Register
#define AT91C_TC0_IER   ((AT91_REG *) 	0xFF014024) // (TC0) Interrupt Enable Register
#define AT91C_TC0_RA    ((AT91_REG *) 	0xFF014014) // (TC0) Register A
#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFF014004) // (TC0) Channel Mode Register
#define AT91C_TC0_SR    ((AT91_REG *) 	0xFF014020) // (TC0) Status Register
#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFF014000) // (TC0) Channel Control Register
#define AT91C_TC0_RC    ((AT91_REG *) 	0xFF01401C) // (TC0) Register C
#define AT91C_TC0_RB    ((AT91_REG *) 	0xFF014018) // (TC0) Register B
#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFF014028) // (TC0) Interrupt Disable Register
#define AT91C_TC0_CVR   ((AT91_REG *) 	0xFF014010) // (TC0) Counter Value Register
// ========== Register definition for TCB0 peripheral ========== 
#define AT91C_TCB0_BMR  ((AT91_REG *) 	0xFF0140C4) // (TCB0) TC Block Mode Register
#define AT91C_TCB0_BCR  ((AT91_REG *) 	0xFF0140C0) // (TCB0) TC Block Control Register
// ========== Register definition for EMAC1 peripheral ========== 
#define AT91C_EMAC1_LCOL ((AT91_REG *) 	0xFF03805C) // (EMAC1) Late Collision Register
#define AT91C_EMAC1_IMR ((AT91_REG *) 	0xFF038030) // (EMAC1) Interrupt Mask Register
#define AT91C_EMAC1_SCOL ((AT91_REG *) 	0xFF038044) // (EMAC1) Single Collision Frame Register
#define AT91C_EMAC1_HSL ((AT91_REG *) 	0xFF038094) // (EMAC1) Hash Address Low[31:0]
#define AT91C_EMAC1_SA4L ((AT91_REG *) 	0xFF0380B0) // (EMAC1) Specific Address 4 Low, First 4 bytes
#define AT91C_EMAC1_SA1H ((AT91_REG *) 	0xFF03809C) // (EMAC1) Specific Address 1 High, Last 2 bytes
#define AT91C_EMAC1_RJB ((AT91_REG *) 	0xFF038074) // (EMAC1) Receive Jabber Register
#define AT91C_EMAC1_FRA ((AT91_REG *) 	0xFF038040) // (EMAC1) Frames Transmitted OK Register
#define AT91C_EMAC1_ELR ((AT91_REG *) 	0xFF038070) // (EMAC1) Excessive Length Error Register
#define AT91C_EMAC1_MCOL ((AT91_REG *) 	0xFF038048) // (EMAC1) Multiple Collision Frame Register
#define AT91C_EMAC1_TCR ((AT91_REG *) 	0xFF038010) // (EMAC1) Transmit Control Register
#define AT91C_EMAC1_DTE ((AT91_REG *) 	0xFF038058) // (EMAC1) Deferred Transmission Frame Register
#define AT91C_EMAC1_SQEE ((AT91_REG *) 	0xFF03807C) // (EMAC1) SQE Test Error Register
#define AT91C_EMAC1_ALE ((AT91_REG *) 	0xFF038054) // (EMAC1) Alignment Error Register
#define AT91C_EMAC1_CTL ((AT91_REG *) 	0xFF038000) // (EMAC1) Network Control Register
#define AT91C_EMAC1_SA1L ((AT91_REG *) 	0xFF038098) // (EMAC1) Specific Address 1 Low, First 4 bytes
#define AT91C_EMAC1_CSE ((AT91_REG *) 	0xFF038064) // (EMAC1) Carrier Sense Error Register
#define AT91C_EMAC1_RBQP ((AT91_REG *) 	0xFF038018) // (EMAC1) Receive Buffer Queue Pointer
#define AT91C_EMAC1_DRFC ((AT91_REG *) 	0xFF038080) // (EMAC1) Discarded RX Frame Register
#define AT91C_EMAC1_USF ((AT91_REG *) 	0xFF038078) // (EMAC1) Undersize Frame Register
#define AT91C_EMAC1_CFG ((AT91_REG *) 	0xFF038004) // (EMAC1) Network Configuration Register
#define AT91C_EMAC1_SA3H ((AT91_REG *) 	0xFF0380AC) // (EMAC1) Specific Address 3 High, Last 2 bytes
#define AT91C_EMAC1_CDE ((AT91_REG *) 	0xFF03806C) // (EMAC1) Code Error Register
#define AT91C_EMAC1_IDR ((AT91_REG *) 	0xFF03802C) // (EMAC1) Interrupt Disable Register
#define AT91C_EMAC1_RSR ((AT91_REG *) 	0xFF038020) // (EMAC1) Receive Status Register
#define AT91C_EMAC1_SEQE ((AT91_REG *) 	0xFF038050) // (EMAC1) Frame Check Sequence Error Register
#define AT91C_EMAC1_TSR ((AT91_REG *) 	0xFF038014) // (EMAC1) Transmit Status Register
#define AT91C_EMAC1_OK  ((AT91_REG *) 	0xFF03804C) // (EMAC1) Frames Received OK Register
#define AT91C_EMAC1_SR  ((AT91_REG *) 	0xFF038008) // (EMAC1) Network Status Register
#define AT91C_EMAC1_SA3L ((AT91_REG *) 	0xFF0380A8) // (EMAC1) Specific Address 3 Low, First 4 bytes
#define AT91C_EMAC1_TAR ((AT91_REG *) 	0xFF03800C) // (EMAC1) Transmit Address Register
#define AT91C_EMAC1_TUE ((AT91_REG *) 	0xFF038068) // (EMAC1) Transmit Underrun Error Register
#define AT91C_EMAC1_ISR ((AT91_REG *) 	0xFF038024) // (EMAC1) Interrupt Status Register
#define AT91C_EMAC1_IER ((AT91_REG *) 	0xFF038028) // (EMAC1) Interrupt Enable Register
#define AT91C_EMAC1_HSH ((AT91_REG *) 	0xFF038090) // (EMAC1) Hash Address High[63:32]
#define AT91C_EMAC1_MAN ((AT91_REG *) 	0xFF038034) // (EMAC1) PHY Maintenance Register
#define AT91C_EMAC1_SA2L ((AT91_REG *) 	0xFF0380A0) // (EMAC1) Specific Address 2 Low, First 4 bytes
#define AT91C_EMAC1_SA4H ((AT91_REG *) 	0xFF0380B4) // (EMAC1) Specific Address 4 High, Last 2 bytesr
#define AT91C_EMAC1_SA2H ((AT91_REG *) 	0xFF0380A4) // (EMAC1) Specific Address 2 High, Last 2 bytes
#define AT91C_EMAC1_ECOL ((AT91_REG *) 	0xFF038060) // (EMAC1) Excessive Collision Register
// ========== Register definition for EMAC0 peripheral ========== 
#define AT91C_EMAC0_HSL ((AT91_REG *) 	0xFF034094) // (EMAC0) Hash Address Low[31:0]
#define AT91C_EMAC0_ECOL ((AT91_REG *) 	0xFF034060) // (EMAC0) Excessive Collision Register
#define AT91C_EMAC0_CDE ((AT91_REG *) 	0xFF03406C) // (EMAC0) Code Error Register
#define AT91C_EMAC0_SA3H ((AT91_REG *) 	0xFF0340AC) // (EMAC0) Specific Address 3 High, Last 2 bytes
#define AT91C_EMAC0_SR  ((AT91_REG *) 	0xFF034008) // (EMAC0) Network Status Register
#define AT91C_EMAC0_SA2H ((AT91_REG *) 	0xFF0340A4) // (EMAC0) Specific Address 2 High, Last 2 bytes
#define AT91C_EMAC0_SA1L ((AT91_REG *) 	0xFF034098) // (EMAC0) Specific Address 1 Low, First 4 bytes
#define AT91C_EMAC0_RSR ((AT91_REG *) 	0xFF034020) // (EMAC0) Receive Status Register
#define AT91C_EMAC0_OK  ((AT91_REG *) 	0xFF03404C) // (EMAC0) Frames Received OK Register
#define AT91C_EMAC0_IER ((AT91_REG *) 	0xFF034028) // (EMAC0) Interrupt Enable Register
#define AT91C_EMAC0_USF ((AT91_REG *) 	0xFF034078) // (EMAC0) Undersize Frame Register
#define AT91C_EMAC0_SA1H ((AT91_REG *) 	0xFF03409C) // (EMAC0) Specific Address 1 High, Last 2 bytes
#define AT91C_EMAC0_TUE ((AT91_REG *) 	0xFF034068) // (EMAC0) Transmit Underrun Error Register
#define AT91C_EMAC0_ISR ((AT91_REG *) 	0xFF034024) // (EMAC0) Interrupt Status Register
#define AT91C_EMAC0_SEQE ((AT91_REG *) 	0xFF034050) // (EMAC0) Frame Check Sequence Error Register
#define AT91C_EMAC0_ALE ((AT91_REG *) 	0xFF034054) // (EMAC0) Alignment Error Register
#define AT91C_EMAC0_IDR ((AT91_REG *) 	0xFF03402C) // (EMAC0) Interrupt Disable Register
#define AT91C_EMAC0_CSE ((AT91_REG *) 	0xFF034064) // (EMAC0) Carrier Sense Error Register
#define AT91C_EMAC0_TSR ((AT91_REG *) 	0xFF034014) // (EMAC0) Transmit Status Register
#define AT91C_EMAC0_SA3L ((AT91_REG *) 	0xFF0340A8) // (EMAC0) Specific Address 3 Low, First 4 bytes
#define AT91C_EMAC0_MAN ((AT91_REG *) 	0xFF034034) // (EMAC0) PHY Maintenance Register
#define AT91C_EMAC0_TAR ((AT91_REG *) 	0xFF03400C) // (EMAC0) Transmit Address Register
#define AT91C_EMAC0_SQEE ((AT91_REG *) 	0xFF03407C) // (EMAC0) SQE Test Error Register
#define AT91C_EMAC0_RJB ((AT91_REG *) 	0xFF034074) // (EMAC0) Receive Jabber Register
#define AT91C_EMAC0_SA4H ((AT91_REG *) 	0xFF0340B4) // (EMAC0) Specific Address 4 High, Last 2 bytesr
#define AT91C_EMAC0_CFG ((AT91_REG *) 	0xFF034004) // (EMAC0) Network Configuration Register
#define AT91C_EMAC0_HSH ((AT91_REG *) 	0xFF034090) // (EMAC0) Hash Address High[63:32]
#define AT91C_EMAC0_RBQP ((AT91_REG *) 	0xFF034018) // (EMAC0) Receive Buffer Queue Pointer
#define AT91C_EMAC0_SA4L ((AT91_REG *) 	0xFF0340B0) // (EMAC0) Specific Address 4 Low, First 4 bytes
#define AT91C_EMAC0_SCOL ((AT91_REG *) 	0xFF034044) // (EMAC0) Single Collision Frame Register
#define AT91C_EMAC0_DTE ((AT91_REG *) 	0xFF034058) // (EMAC0) Deferred Transmission Frame Register
#define AT91C_EMAC0_IMR ((AT91_REG *) 	0xFF034030) // (EMAC0) Interrupt Mask Register
#define AT91C_EMAC0_CTL ((AT91_REG *) 	0xFF034000) // (EMAC0) Network Control Register
#define AT91C_EMAC0_TCR ((AT91_REG *) 	0xFF034010) // (EMAC0) Transmit Control Register
#define AT91C_EMAC0_LCOL ((AT91_REG *) 	0xFF03405C) // (EMAC0) Late Collision Register
#define AT91C_EMAC0_ELR ((AT91_REG *) 	0xFF034070) // (EMAC0) Excessive Length Error Register
#define AT91C_EMAC0_FRA ((AT91_REG *) 	0xFF034040) // (EMAC0) Frames Transmitted OK Register
#define AT91C_EMAC0_MCOL ((AT91_REG *) 	0xFF034048) // (EMAC0) Multiple Collision Frame Register
#define AT91C_EMAC0_SA2L ((AT91_REG *) 	0xFF0340A0) // (EMAC0) Specific Address 2 Low, First 4 bytes
#define AT91C_EMAC0_DRFC (