📄 ddi_display_controller_ssd1289.c
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u32Data1 <<= 16;
break;
case SWAP_ALL_BYTES: // Swap bytes 0,3 and 1,2
// Move command byte to upper half of upper 16-bit word
u32Command <<= 24;
u32Data0 <<= 24;
u32Data1 <<= 24;
break;
default:
SystemHalt(); // Programming error
}
if(eCommMode==CMD_MODE)
{
// 8- and 16-bit bus have same command sizes
#ifdef DEBUG
ret1 =
#endif
ddi_lcdif_WriteDirect(eCommMode, (void *)&u32Command, sizeof(DDI_DISPLAY_WORD_TYPE));
}
else if(eCommMode==DATA_MODE)
{
if(WORDLENGTH_8BITS == hw_lcdif_GetWordLength())
{
// For 8-bit, we need to send data in two 8 bit parts
#ifdef DEBUG
ret1 =
#endif
ddi_lcdif_WriteDirect(eCommMode, (void *)&u32Data1, sizeof(DDI_DISPLAY_WORD_TYPE));
#ifdef DEBUG
ret2 =
#endif
ddi_lcdif_WriteDirect(eCommMode, (void *)&u32Data0, sizeof(DDI_DISPLAY_WORD_TYPE));
}
else
{
// For 16-bit, data is ok as 16 bits
#ifdef DEBUG
ret1 =
#endif
ddi_lcdif_WriteDirect(eCommMode, (void *)&u32Command, sizeof(DDI_DISPLAY_WORD_TYPE));
}
}
#ifdef DEBUG
assert(!ret1);
assert(!ret2);
#endif
}
////////////////////////////////////////////////////////////////////////////////
//! \fn RtStatus_t ddi_display_controller_GetLcdifInitStruct(hw_lcdif_Init_t *pInit, gfx_BitmapTypeEnum_t eBitmapType)
//!
//! \brief Copies the LCDIF init struct that corresponds to the given color format
//!
//! \fntype Function
//!
//! \param[in,out] pInit - Pointer to init struct to copy to
//! \param[in] eBitmapType - Graphics color format specifier
//!
//! \retval SUCCESS No error
//!
//! \retval ERROR_DDI_DISPLAY_CONTROLLER_BITMAP_TYPE_UNSUPPORTED - This
//! controller does not support the given bitmap color type
//!
//! This function is implemented per controller or display. The appropriate
//! LCDIF init parameters are copied to the given init struct pointer according
//! to the type of color format is specified. Not all controllers/displays are
//! capable of all color formats, so this function may return an error
//! indicating that the given color format is not supported.
//!
////////////////////////////////////////////////////////////////////////////////
RtStatus_t ddi_display_controller_GetLcdifInitStruct(hw_lcdif_Init_t *pInit, gfx_BitmapTypeEnum_t eBitmapType)
{
//! Init structure for LCDIF, may be loaded from a resource
hw_lcdif_Init_t LcdifInit =
{
//! No busy line, no byte-swapping, bring LCD module out of reset
false, //! m_bBusyEnable
DDI_DISPLAY_DATA_SWIZZLE, //! m_eDataSwizzle
LCDRESET_HIGH, //! m_eReset
BUSMODE_8080, //! m_eBusMode
DDI_DISPLAY_WORDLENGTH, //! m_eWordLength
//! Bus timing info
//! 1XCLK ~= 168ns
{
DDI_DISPLAY_DATA_SETUP_XCLKS, //! m_u8DataSetup
DDI_DISPLAY_DATA_HOLD_XCLKS, //! m_u8DataHold
DDI_DISPLAY_CMD_SETUP_XCLKS, //! m_u8CmdSetup
DDI_DISPLAY_CMD_HOLD_XCLKS, //! m_u8CmdHold
}
};
if( BITMAP_TYPE_16BPP_565 != eBitmapType )
return ERROR_DDI_DISPLAY_CONTROLLER_BITMAP_TYPE_UNSUPPORTED;
memcpy(pInit, &LcdifInit, sizeof(hw_lcdif_Init_t));
return SUCCESS;
}
////////////////////////////////////////////////////////////////////////////////
//! \fn static void InitPwmBacklight(void)
//!
//! \brief Sets up the PWM backlight control signal
//!
//! \fntype Function
//!
//! Inits the PWM hardware block and sets up the GPIOs for PWM mode.
//! The initial backlight frequency is set, but the duty cycle is set to zero
//!
////////////////////////////////////////////////////////////////////////////////
static void InitPwmBacklight(void)
{
// Do a raw init of the PWM GPIO
if( !ddi_etm_IsPresent() ) {
HW_PINCTRL_MUXSEL6_CLR(0x00300000 << (2*DDI_DISPLAY_BACKLIGHT_PWM_CHANNEL));
}
// Set up the backlight
BF_CLR(PWM_CTRL, SFTRST);
BF_CLR(PWM_CTRL, CLKGATE);
// Initialize to 0% duty cycle
HW_PWMn_ACTIVE_WR(DDI_DISPLAY_BACKLIGHT_PWM_CHANNEL, 0);
BF_CS5n(PWMn_PERIOD, DDI_DISPLAY_BACKLIGHT_PWM_CHANNEL,
MATT, 0,
CDIV, BACKLIGHT_PWM_CDIV,
INACTIVE_STATE, BV_PWMn_PERIOD_INACTIVE_STATE__0,
ACTIVE_STATE, BV_PWMn_PERIOD_ACTIVE_STATE__1,
PERIOD, BACKLIGHT_PWM_PERIOD);
HW_PWM_CTRL_CLR(1 << DDI_DISPLAY_BACKLIGHT_PWM_CHANNEL);
}
////////////////////////////////////////////////////////////////////////////////
//! \fn static void SendControllerInitSeq(gfx_BitmapTypeEnum_t eBitmapType, uint32_t u32Width, uint32_t u32Height)
//!
//! \brief Sends commands to initialize the controller from reset
//!
//! \fntype Function
//!
//! \param[in] eBitmapType - Graphics color format specifier
//! \param[in] u32Width - Desired screen width setting
//! \param[in] u32Height - Desired screen height setting
//!
//! This function sends commands to initialize the controller after it has
//! been taken out of reset.
//!
//! \retval SUCCESS No error
//!
//! \retval ERROR_DDI_DISPLAY_CONTROLLER_BITMAP_TYPE_UNSUPPORTED - This
//! controller does not support the given bitmap color type
//!
//! \retval ERROR_DDI_DISPLAY_CONTROLLER_SCREEN_SIZE - This
//! controller does not support the given screen dimensions
//!
////////////////////////////////////////////////////////////////////////////////
static void SendControllerInitSeq(gfx_BitmapTypeEnum_t eBitmapType, uint32_t u32Width, uint32_t u32Height)
{
// Init commands for the LCD hardware
WriteDirect(CMD_MODE, 0x00); // Start oscillation
WriteDirect(DATA_MODE, 0x0001); // OSCEN=1
WriteDirect(CMD_MODE, 0x03); // Power Control 1
WriteDirect(DATA_MODE, 0xa8a4);
WriteDirect(CMD_MODE, 0x0c); // Power Control 2
WriteDirect(DATA_MODE, 0x0000);
WriteDirect(CMD_MODE, 0x0d); // Power Control 3
WriteDirect(DATA_MODE, 0x030c);
WriteDirect(CMD_MODE, 0x0e); // Power Control 4
WriteDirect(DATA_MODE, 0x2d00);
WriteDirect(CMD_MODE, 0x1e); // Power Control 5
WriteDirect(DATA_MODE, 0x00b0);
WriteDirect(CMD_MODE, 0x01); // Driver Output Control
WriteDirect(DATA_MODE, 0x693f); // RL=1, REV=1, BGR=1, TB=1
// Restore VSYNC mode from low power state
WriteDirect(CMD_MODE, 0x02); // LCD Driving Waveform Control
WriteDirect(DATA_MODE, 0x0600);
WriteDirect(CMD_MODE, 0x10); // Sleep Mode
WriteDirect(DATA_MODE, 0x0000);
WriteDirect(CMD_MODE, 0x11); // Entry Mode
WriteDirect(DATA_MODE, 0x6018); // 16bpp 565 mode, ID[1:0] = 01, AM = 1
// Horz increment, Vert decrement
WriteDirect(CMD_MODE, 0x05); // Compare register
WriteDirect(DATA_MODE, 0x0000);
WriteDirect(CMD_MODE, 0x06); // Compare register
WriteDirect(DATA_MODE, 0x0000);
// Horizontal and Vertical porch are for DOTCLK mode operation
WriteDirect(CMD_MODE, 0x16); // Horizontal Porch
WriteDirect(DATA_MODE, 0xEF1C);
WriteDirect(CMD_MODE, 0x17); // Vertical Porch
WriteDirect(DATA_MODE, 0x0003);
WriteDirect(CMD_MODE, 0x07); // Display Control
WriteDirect(DATA_MODE, 0x0231); // Output disabled
WriteDirect(CMD_MODE, 0x0b); // Frame Cycle Control
WriteDirect(DATA_MODE, 0x0000);
WriteDirect(CMD_MODE, 0x0F); // Gate Scan Position
WriteDirect(DATA_MODE, 0x0000);
WriteDirect(CMD_MODE, 0x41); // Vertical Scroll Control
WriteDirect(DATA_MODE, 0x0000);
WriteDirect(CMD_MODE, 0x42); // Vertical Scroll Control
WriteDirect(DATA_MODE, 0x0000);
WriteDirect(CMD_MODE, 0x48); // 1st Screen driving position
WriteDirect(DATA_MODE, 0x0000);
WriteDirect(CMD_MODE, 0x49); // 1st Screen driving position
WriteDirect(DATA_MODE, 0x013f); // 319 decimal
WriteDirect(CMD_MODE, 0x4a); // 2nd Screen driving position
WriteDirect(DATA_MODE, 0x0000);
WriteDirect(CMD_MODE, 0x4b); // 2nd Screen driving position
WriteDirect(DATA_MODE, 0x0000);
WriteDirect(CMD_MODE, 0x44); // Horizontal RAM address position
WriteDirect(DATA_MODE, 0xef00);
WriteDirect(CMD_MODE, 0x45); // Window Vertical RAM address position
WriteDirect(DATA_MODE, 0x0000);
WriteDirect(CMD_MODE, 0x46); // Window Vertical RAM address position
WriteDirect(DATA_MODE, 0x013f);
WriteDirect(CMD_MODE, 0x30); // Gamma control
WriteDirect(DATA_MODE, 0x0707);
WriteDirect(CMD_MODE, 0x31); // Gamma control
WriteDirect(DATA_MODE, 0x0204);
WriteDirect(CMD_MODE, 0x32); // Gamma control
WriteDirect(DATA_MODE, 0x0204);
WriteDirect(CMD_MODE, 0x33); // Gamma control
WriteDirect(DATA_MODE, 0x0502);
WriteDirect(CMD_MODE, 0x34); // Gamma control
WriteDirect(DATA_MODE, 0x0507);
WriteDirect(CMD_MODE, 0x35); // Gamma control
WriteDirect(DATA_MODE, 0x0204);
WriteDirect(CMD_MODE, 0x36); // Gamma control
WriteDirect(DATA_MODE, 0x0204);
WriteDirect(CMD_MODE, 0x37); // Gamma control
WriteDirect(DATA_MODE, 0x0502);
WriteDirect(CMD_MODE, 0x3a); // Gamma control
WriteDirect(DATA_MODE, 0x0302);
WriteDirect(CMD_MODE, 0x3b); // Gamma control
WriteDirect(DATA_MODE, 0x0302);
WriteDirect(CMD_MODE, 0x23); // RAM write data mask
WriteDirect(DATA_MODE, 0x0000);
WriteDirect(CMD_MODE, 0x24); // RAM write data mask
WriteDirect(DATA_MODE, 0x0000);
}
/*
#ifdef RTOS_THREADX // VSYNC only supported in threadx builds
////////////////////////////////////////////////////////////////////////////////
//! \fn static void ddi_display_controllerVsyncIsr(void *)
//!
//! \brief Services the VSYNC interrupt
//!
//! \fntype Deferred service routine
//!
//! This function signals the occurrence of the VSYNC signal. The VSYNC event
//! is signalled via semaphore.
//!
////////////////////////////////////////////////////////////////////////////////
static void ddi_display_controller_VsyncIsr(void *vUnused)
{
// Check to see if this is our interrupt
if( CHECK_VSYNC_IRQ_STATUS() )
{
// Put the VSYNC semaphore as a binary semaphore
// There only ever needs to be at most one instance
tx_semaphore_put(pVideoSemaphore);
// Disable and clear the interrupt
DISABLE_VSYNC_IRQ();
CLEAR_VSYNC_IRQ_STATUS();
}
// If it's not our interrupt, ignore this
}
*/
////////////////////////////////////////////////////////////////////////////////
//! \fn static RtStatus_t WaitForControllerVsync(void)
//!
//! \brief Blocks until the next valid VSYNC edge
//!
//! \fntype Function
//!
//! In VSYNC mode, this command will block the calling thread until the next
//! valid VSYNC edge or until the timeout period has elapsed.
//!
////////////////////////////////////////////////////////////////////////////////
/*
static RtStatus_t WaitForControllerVsync(void)
{
RtStatus_t ret = SUCCESS;
uint32_t u32Ret;
if( ddi_etm_IsPresent() ) {
return SUCCESS;
}
// Check if our semaphore was created
if( g_ddi_display_VideoMode == DDI_DISPLAY_VSYNC_MODE && pVideoSemaphore )
{
// Enable the interrupt vector
hw_icoll_EnableVector(GPIO_VSYNC_IRQ_VECTOR, true);
// Now enable the VSYNC ISR, it will put the binary semaphore on the
// next VSYNC edge
ENABLE_VSYNC_IRQ();
// Block on the VSYNC signal
u32Ret = tx_semaphore_get(pVideoSemaphore, VSYNC_TIMEOUT_TICKS);
if( u32Ret )
{
ret = CONVERT_TX_RTCODE(u32Ret);
if( ERROR_OS_KERNEL_TX_NO_INSTANCE == ret )
{
// There was an error with the VSYNC signal reception
ret = ERROR_DDI_DISPLAY_CONTROLLER_VSYNC;
}
}
}
else
{
// Not our ISR, we're not configured for VSYNC mode
ret = ERROR_DDI_DISPLAY_CONTROLLER_VSYNC;
}
return ret;
}
*/
////////////////////////////////////////////////////////////////////////////////
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