fsk.tan.rpt

... ..应该有些用处.对于爱好EDA开发的人来说

; Slack ; Required tsu ; Actual tsu ; From  ; To              ; To Clock ;
+-------+--------------+------------+-------+-----------------+----------+
; N/A   ; None         ; 2.672 ns   ; start ; f2              ; clk      ;
; N/A   ; None         ; 2.672 ns   ; start ; f1              ; clk      ;
; N/A   ; None         ; 2.476 ns   ; start ; q1[2]           ; clk      ;
; N/A   ; None         ; 2.474 ns   ; start ; q1[3]           ; clk      ;
; N/A   ; None         ; 2.474 ns   ; start ; q1[1]           ; clk      ;
; N/A   ; None         ; 2.323 ns   ; x     ; y~reg0          ; clk      ;
; N/A   ; None         ; 2.117 ns   ; start ; q2[0]           ; clk      ;
; N/A   ; None         ; 2.117 ns   ; start ; q2[0]~DUPLICATE ; clk      ;
+-------+--------------+------------+-------+-----------------+----------+


+--------------------------------------------------------------+
; tco                                                          ;
+-------+--------------+------------+--------+----+------------+
; Slack ; Required tco ; Actual tco ; From   ; To ; From Clock ;
+-------+--------------+------------+--------+----+------------+
; N/A   ; None         ; 5.053 ns   ; y~reg0 ; y  ; clk        ;
+-------+--------------+------------+--------+----+------------+


+------------------------------------------------------------------------------+
; th                                                                           ;
+---------------+-------------+-----------+-------+-----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To              ; To Clock ;
+---------------+-------------+-----------+-------+-----------------+----------+
; N/A           ; None        ; -1.878 ns ; start ; q2[0]           ; clk      ;
; N/A           ; None        ; -1.878 ns ; start ; q2[0]~DUPLICATE ; clk      ;
; N/A           ; None        ; -2.084 ns ; x     ; y~reg0          ; clk      ;
; N/A           ; None        ; -2.235 ns ; start ; q1[3]           ; clk      ;
; N/A           ; None        ; -2.235 ns ; start ; q1[1]           ; clk      ;
; N/A           ; None        ; -2.237 ns ; start ; q1[2]           ; clk      ;
; N/A           ; None        ; -2.433 ns ; start ; f2              ; clk      ;
; N/A           ; None        ; -2.433 ns ; start ; f1              ; clk      ;
+---------------+-------------+-----------+-------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Wed Apr 16 12:19:02 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fsk -c fsk --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 500.0 MHz between source register "q1[1]" and destination register "q1[2]"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.857 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y10_N21; Fanout = 4; REG Node = 'q1[1]'
            Info: 2: + IC(0.356 ns) + CELL(0.346 ns) = 0.702 ns; Loc. = LCCOMB_X39_Y10_N12; Fanout = 1; COMB Node = 'q1~159'
            Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.857 ns; Loc. = LCFF_X39_Y10_N13; Fanout = 3; REG Node = 'q1[2]'
            Info: Total cell delay = 0.501 ns ( 58.46 % )
            Info: Total interconnect delay = 0.356 ns ( 41.54 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.493 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.678 ns) + CELL(0.618 ns) = 2.493 ns; Loc. = LCFF_X39_Y10_N13; Fanout = 3; REG Node = 'q1[2]'
                Info: Total cell delay = 1.472 ns ( 59.05 % )
                Info: Total interconnect delay = 1.021 ns ( 40.95 % )
            Info: - Longest clock path from clock "clk" to source register is 2.493 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.678 ns) + CELL(0.618 ns) = 2.493 ns; Loc. = LCFF_X39_Y10_N21; Fanout = 4; REG Node = 'q1[1]'
                Info: Total cell delay = 1.472 ns ( 59.05 % )
                Info: Total interconnect delay = 1.021 ns ( 40.95 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: tsu for register "f2" (data pin = "start", clock pin = "clk") is 2.672 ns
    Info: + Longest pin to register delay is 5.075 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N4; Fanout = 7; PIN Node = 'start'
        Info: 2: + IC(3.475 ns) + CELL(0.746 ns) = 5.075 ns; Loc. = LCFF_X39_Y10_N19; Fanout = 1; REG Node = 'f2'
        Info: Total cell delay = 1.600 ns ( 31.53 % )
        Info: Total interconnect delay = 3.475 ns ( 68.47 % )
    Info: + Micro setup delay of destination is 0.090 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.493 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.678 ns) + CELL(0.618 ns) = 2.493 ns; Loc. = LCFF_X39_Y10_N19; Fanout = 1; REG Node = 'f2'
        Info: Total cell delay = 1.472 ns ( 59.05 % )
        Info: Total interconnect delay = 1.021 ns ( 40.95 % )
Info: tco from clock "clk" to destination pin "y" through register "y~reg0" is 5.053 ns
    Info: + Longest clock path from clock "clk" to source register is 2.493 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.678 ns) + CELL(0.618 ns) = 2.493 ns; Loc. = LCFF_X39_Y10_N17; Fanout = 1; REG Node = 'y~reg0'
        Info: Total cell delay = 1.472 ns ( 59.05 % )
        Info: Total interconnect delay = 1.021 ns ( 40.95 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Longest register to pin delay is 2.466 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y10_N17; Fanout = 1; REG Node = 'y~reg0'
        Info: 2: + IC(0.322 ns) + CELL(2.144 ns) = 2.466 ns; Loc. = PIN_N1; Fanout = 0; PIN Node = 'y'
        Info: Total cell delay = 2.144 ns ( 86.94 % )
        Info: Total interconnect delay = 0.322 ns ( 13.06 % )
Info: th for register "q2[0]" (data pin = "start", clock pin = "clk") is -1.878 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.493 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.678 ns) + CELL(0.618 ns) = 2.493 ns; Loc. = LCFF_X39_Y10_N25; Fanout = 3; REG Node = 'q2[0]'
        Info: Total cell delay = 1.472 ns ( 59.05 % )
        Info: Total interconnect delay = 1.021 ns ( 40.95 % )
    Info: + Micro hold delay of destination is 0.149 ns
    Info: - Shortest pin to register delay is 4.520 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N4; Fanout = 7; PIN Node = 'start'
        Info: 2: + IC(3.458 ns) + CELL(0.053 ns) = 4.365 ns; Loc. = LCCOMB_X39_Y10_N24; Fanout = 1; COMB Node = 'q1~157'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 4.520 ns; Loc. = LCFF_X39_Y10_N25; Fanout = 3; REG Node = 'q2[0]'
        Info: Total cell delay = 1.062 ns ( 23.50 % )
        Info: Total interconnect delay = 3.458 ns ( 76.50 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 120 megabytes of memory during processing
    Info: Processing ended: Wed Apr 16 12:19:03 2008
    Info: Elapsed time: 00:00:01