fsk.map.rpt

... ..应该有些用处.对于爱好EDA开发的人来说

; Block Design Naming                                                         ; Auto               ; Auto               ;
+-----------------------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                   ;
+----------------------------------+-----------------+-----------------+-----------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path      ;
+----------------------------------+-----------------+-----------------+-----------------------------------+
; fsk.vhd                          ; yes             ; User VHDL File  ; D:/文档/bishe/FSK调制程序/fsk.vhd ;
+----------------------------------+-----------------+-----------------+-----------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+-----------------------------------------------+-------+
; Resource                                      ; Usage ;
+-----------------------------------------------+-------+
; Estimated ALUTs Used                          ; 7     ;
; Dedicated logic registers                     ; 7     ;
;                                               ;       ;
; Estimated ALUTs Unavailable                   ; 2     ;
;                                               ;       ;
; Total combinational functions                 ; 7     ;
; Combinational ALUT usage by number of inputs  ;       ;
;     -- 7 input functions                      ; 0     ;
;     -- 6 input functions                      ; 0     ;
;     -- 5 input functions                      ; 2     ;
;     -- 4 input functions                      ; 0     ;
;     -- <=3 input functions                    ; 5     ;
;                                               ;       ;
; Combinational ALUTs by mode                   ;       ;
;     -- normal mode                            ; 7     ;
;     -- extended LUT mode                      ; 0     ;
;     -- arithmetic mode                        ; 0     ;
;     -- shared arithmetic mode                 ; 0     ;
;                                               ;       ;
; Estimated ALUT/register pairs used            ; 9     ;
;                                               ;       ;
; Total registers                               ; 7     ;
;     -- Dedicated logic registers              ; 7     ;
;     -- I/O registers                          ; 0     ;
;                                               ;       ;
; Estimated ALMs:  partially or completely used ; 5     ;
;                                               ;       ;
; I/O pins                                      ; 4     ;
; Maximum fan-out node                          ; clk   ;
; Maximum fan-out                               ; 7     ;
; Total fan-out                                 ; 39    ;
; Average fan-out                               ; 2.17  ;
+-----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                           ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; |fsk                       ; 7 (7)             ; 7 (7)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 4    ; 0            ; |fsk                ; work         ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; q2[1]                                 ; Stuck at GND due to stuck port data_in ;
; q1[0]                                 ; Merged with q2[0]                      ;
; Total Number of Removed Registers = 2 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 7     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 2     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 4:1                ; 4 bits    ; 8 ALUTs       ; 8 ALUTs              ; 0 ALUTs                ; Yes        ; |fsk|q1[3]                 ;
; 4:1                ; 2 bits    ; 4 ALUTs       ; 4 ALUTs              ; 0 ALUTs                ; Yes        ; |fsk|q2[0]                 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Wed Apr 16 12:18:33 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fsk -c fsk
Info: Found 2 design units, including 1 entities, in source file fsk.vhd
    Info: Found design unit 1: fsk-behav
    Info: Found entity 1: fsk
Info: Elaborating entity "fsk" for the top level hierarchy
Warning (14130): Reduced register "q2[1]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "q1[0]" merged to single register "q2[0]"
Info: Implemented 11 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 1 output pins
    Info: Implemented 7 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Allocated 165 megabytes of memory during processing
    Info: Processing ended: Wed Apr 16 12:18:37 2008
    Info: Elapsed time: 00:00:04