fsk.vhd

来自「... ..应该有些用处.对于爱好EDA开发的人来说」· VHDL 代码 · 共 45 行

library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fsk is
     port(clk :in std_logic;
          start :in std_logic;
          x :in std_logic;
          y :out std_logic);
end fsk;

architecture behav of fsk is
     signal q1:integer range 0 to 11;
     signal q2:integer range 0 to 3;
     signal f1,f2:std_logic;
begin
process(clk)
begin
    if clk'event and clk='1' then
         if start='0' then q1<=0;
         elsif q1<=5 then f1<='1';q1<=q1+1;
         elsif q1=11 then f1<='0';q1<=0;
         else f1<='0';q1<=q1+1;
         end if;
    end if;
end process;
process(clk)
begin
  if clk'event and clk='1' then
       if start='0' then q2<=0;
       elsif q2<=0 then f2<='1';q2<=q2+1;
       elsif q2=1 then f2<='0';q2<=0;
       else f2<='0';q2<=q2+1;
       end if;
  end if;
end process;
process(clk,x)
begin
    if clk'event and clk='1' then
       if x='0' then y<=f1;
       else y<=f2;
       end if;
    end if;
end process;
end behav;