fsk2.vhd

来自「... ..应该有些用处.对于爱好EDA开发的人来说」· VHDL 代码 · 共 36 行

library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fsk2 is
     port(clk :in std_logic;
          start :in std_logic;
          x :in std_logic;
          y :out std_logic);
end fsk2;

architecture behav of fsk2 is
signal q:integer range 0 to 11;
signal xx:std_logic;
signal m:integer range 0 to 5;
begin
process(clk)
begin
    if clk'event and clk='1' then xx<=x;
         if start='0' then q<=0;
         elsif q=11 then q<=0;
         else q<=q+1;
         end if;
    end if;
end process;
process(xx,q)
begin
    if q=11 then m<=0;
    elsif q=10 then
        if m<=3 then y<='0';
        else y<='1';
        end if;
    elsif xx'event and xx='1' then m<=m+1;
    end if;
end process;
end behav;