fsk2.tan.qmsg

... ..应该有些用处.对于爱好EDA开发的人来说

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "q\[2\] m\[2\] clk 1.031 ns " "Info: Found hold time violation between source  pin or register \"q\[2\]\" and destination pin or register \"m\[2\]\" for clock \"clk\" (Hold time is 1.031 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "2.710 ns + Largest " "Info: + Largest clock skew is 2.710 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.214 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 5.214 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns clk 1 CLK PIN_W21 5 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_W21; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.046 ns) + CELL(0.712 ns) 2.598 ns xx 2 REG LCFF_X14_Y2_N9 1 " "Info: 2: + IC(1.046 ns) + CELL(0.712 ns) = 2.598 ns; Loc. = LCFF_X14_Y2_N9; Fanout = 1; REG Node = 'xx'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.758 ns" { clk xx } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.359 ns) + CELL(0.000 ns) 3.957 ns xx~clkctrl 3 COMB CLKCTRL_G6 3 " "Info: 3: + IC(1.359 ns) + CELL(0.000 ns) = 3.957 ns; Loc. = CLKCTRL_G6; Fanout = 3; COMB Node = 'xx~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.359 ns" { xx xx~clkctrl } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.639 ns) + CELL(0.618 ns) 5.214 ns m\[2\] 4 REG LCFF_X14_Y2_N31 2 " "Info: 4: + IC(0.639 ns) + CELL(0.618 ns) = 5.214 ns; Loc. = LCFF_X14_Y2_N31; Fanout = 2; REG Node = 'm\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.257 ns" { xx~clkctrl m[2] } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.170 ns ( 41.62 % ) " "Info: Total cell delay = 2.170 ns ( 41.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.044 ns ( 58.38 % ) " "Info: Total interconnect delay = 3.044 ns ( 58.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.214 ns" { clk xx xx~clkctrl m[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.214 ns" { clk {} clk~combout {} xx {} xx~clkctrl {} m[2] {} } { 0.000ns 0.000ns 1.046ns 1.359ns 0.639ns } { 0.000ns 0.840ns 0.712ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.504 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.504 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns clk 1 CLK PIN_W21 5 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_W21; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.046 ns) + CELL(0.618 ns) 2.504 ns q\[2\] 2 REG LCFF_X14_Y2_N15 4 " "Info: 2: + IC(1.046 ns) + CELL(0.618 ns) = 2.504 ns; Loc. = LCFF_X14_Y2_N15; Fanout = 4; REG Node = 'q\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.664 ns" { clk q[2] } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.458 ns ( 58.23 % ) " "Info: Total cell delay = 1.458 ns ( 58.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.046 ns ( 41.77 % ) " "Info: Total interconnect delay = 1.046 ns ( 41.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.504 ns" { clk q[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.504 ns" { clk {} clk~combout {} q[2] {} } { 0.000ns 0.000ns 1.046ns } { 0.000ns 0.840ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.214 ns" { clk xx xx~clkctrl m[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.214 ns" { clk {} clk~combout {} xx {} xx~clkctrl {} m[2] {} } { 0.000ns 0.000ns 1.046ns 1.359ns 0.639ns } { 0.000ns 0.840ns 0.712ns 0.000ns 0.618ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.504 ns" { clk q[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.504 ns" { clk {} clk~combout {} q[2] {} } { 0.000ns 0.000ns 1.046ns } { 0.000ns 0.840ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns - " "Info: - Micro clock to output delay of source is 0.094 ns" {  } { { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.734 ns - Shortest register register " "Info: - Shortest register to register delay is 1.734 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[2\] 1 REG LCFF_X14_Y2_N15 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y2_N15; Fanout = 4; REG Node = 'q\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { q[2] } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.914 ns) + CELL(0.053 ns) 0.967 ns Equal1~17 2 COMB LCCOMB_X14_Y2_N24 4 " "Info: 2: + IC(0.914 ns) + CELL(0.053 ns) = 0.967 ns; Loc. = LCCOMB_X14_Y2_N24; Fanout = 4; COMB Node = 'Equal1~17'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.967 ns" { q[2] Equal1~17 } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.266 ns) + CELL(0.346 ns) 1.579 ns m\[2\]~154 3 COMB LCCOMB_X14_Y2_N30 1 " "Info: 3: + IC(0.266 ns) + CELL(0.346 ns) = 1.579 ns; Loc. = LCCOMB_X14_Y2_N30; Fanout = 1; COMB Node = 'm\[2\]~154'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.612 ns" { Equal1~17 m[2]~154 } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 1.734 ns m\[2\] 4 REG LCFF_X14_Y2_N31 2 " "Info: 4: + IC(0.000 ns) + CELL(0.155 ns) = 1.734 ns; Loc. = LCFF_X14_Y2_N31; Fanout = 2; REG Node = 'm\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { m[2]~154 m[2] } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.554 ns ( 31.95 % ) " "Info: Total cell delay = 0.554 ns ( 31.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.180 ns ( 68.05 % ) " "Info: Total interconnect delay = 1.180 ns ( 68.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.734 ns" { q[2] Equal1~17 m[2]~154 m[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.734 ns" { q[2] {} Equal1~17 {} m[2]~154 {} m[2] {} } { 0.000ns 0.914ns 0.266ns 0.000ns } { 0.000ns 0.053ns 0.346ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.214 ns" { clk xx xx~clkctrl m[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.214 ns" { clk {} clk~combout {} xx {} xx~clkctrl {} m[2] {} } { 0.000ns 0.000ns 1.046ns 1.359ns 0.639ns } { 0.000ns 0.840ns 0.712ns 0.000ns 0.618ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.504 ns" { clk q[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.504 ns" { clk {} clk~combout {} q[2] {} } { 0.000ns 0.000ns 1.046ns } { 0.000ns 0.840ns 0.618ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.734 ns" { q[2] Equal1~17 m[2]~154 m[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.734 ns" { q[2] {} Equal1~17 {} m[2]~154 {} m[2] {} } { 0.000ns 0.914ns 0.266ns 0.000ns } { 0.000ns 0.053ns 0.346ns 0.155ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "q\[3\] start clk 2.775 ns register " "Info: tsu for register \"q\[3\]\" (data pin = \"start\", clock pin = \"clk\") is 2.775 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.189 ns + Longest pin register " "Info: + Longest pin to register delay is 5.189 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.857 ns) 0.857 ns start 1 PIN PIN_AB15 4 " "Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_AB15; Fanout = 4; PIN Node = 'start'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { start } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.811 ns) + CELL(0.366 ns) 5.034 ns q~154 2 COMB LCCOMB_X14_Y2_N12 1 " "Info: 2: + IC(3.811 ns) + CELL(0.366 ns) = 5.034 ns; Loc. = LCCOMB_X14_Y2_N12; Fanout = 1; COMB Node = 'q~154'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.177 ns" { start q~154 } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.189 ns q\[3\] 3 REG LCFF_X14_Y2_N13 4 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.189 ns; Loc. = LCFF_X14_Y2_N13; Fanout = 4; REG Node = 'q\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { q~154 q[3] } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.378 ns ( 26.56 % ) " "Info: Total cell delay = 1.378 ns ( 26.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.811 ns ( 73.44 % ) " "Info: Total interconnect delay = 3.811 ns ( 73.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.189 ns" { start q~154 q[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.189 ns" { start {} start~combout {} q~154 {} q[3] {} } { 0.000ns 0.000ns 3.811ns 0.000ns } { 0.000ns 0.857ns 0.366ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.504 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.504 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns clk 1 CLK PIN_W21 5 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_W21; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.046 ns) + CELL(0.618 ns) 2.504 ns q\[3\] 2 REG LCFF_X14_Y2_N13 4 " "Info: 2: + IC(1.046 ns) + CELL(0.618 ns) = 2.504 ns; Loc. = LCFF_X14_Y2_N13; Fanout = 4; REG Node = 'q\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.664 ns" { clk q[3] } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.458 ns ( 58.23 % ) " "Info: Total cell delay = 1.458 ns ( 58.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.046 ns ( 41.77 % ) " "Info: Total interconnect delay = 1.046 ns ( 41.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.504 ns" { clk q[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.504 ns" { clk {} clk~combout {} q[3] {} } { 0.000ns 0.000ns 1.046ns } { 0.000ns 0.840ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.189 ns" { start q~154 q[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.189 ns" { start {} start~combout {} q~154 {} q[3] {} } { 0.000ns 0.000ns 3.811ns 0.000ns } { 0.000ns 0.857ns 0.366ns 0.155ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.504 ns" { clk q[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.504 ns" { clk {} clk~combout {} q[3] {} } { 0.000ns 0.000ns 1.046ns } { 0.000ns 0.840ns 0.618ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk y y\$latch 7.608 ns register " "Info: tco from clock \"clk\" to destination pin \"y\" through register \"y\$latch\" is 7.608 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.118 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 5.118 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns clk 1 CLK PIN_W21 5 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_W21; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.046 ns) + CELL(0.712 ns) 2.598 ns q\[1\] 2 REG LCFF_X14_Y2_N17 5 " "Info: 2: + IC(1.046 ns) + CELL(0.712 ns) = 2.598 ns; Loc. = LCFF_X14_Y2_N17; Fanout = 5; REG Node = 'q\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.758 ns" { clk q[1] } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.083 ns) + CELL(0.228 ns) 3.909 ns Equal1~17 3 COMB LCCOMB_X14_Y2_N24 4 " "Info: 3: + IC(1.083 ns) + CELL(0.228 ns) = 3.909 ns; Loc. = LCCOMB_X14_Y2_N24; Fanout = 4; COMB Node = 'Equal1~17'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.311 ns" { q[1] Equal1~17 } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.981 ns) + CELL(0.228 ns) 5.118 ns y\$latch 4 REG LCCOMB_X14_Y2_N28 1 " "Info: 4: + IC(0.981 ns) + CELL(0.228 ns) = 5.118 ns; Loc. = LCCOMB_X14_Y2_N28; Fanout = 1; REG Node = 'y\$latch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.209 ns" { Equal1~17 y$latch } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 26 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.008 ns ( 39.23 % ) " "Info: Total cell delay = 2.008 ns ( 39.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.110 ns ( 60.77 % ) " "Info: Total interconnect delay = 3.110 ns ( 60.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.118 ns" { clk q[1] Equal1~17 y$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.118 ns" { clk {} clk~combout {} q[1] {} Equal1~17 {} y$latch {} } { 0.000ns 0.000ns 1.046ns 1.083ns 0.981ns } { 0.000ns 0.840ns 0.712ns 0.228ns 0.228ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 26 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.490 ns + Longest register pin " "Info: + Longest register to pin delay is 2.490 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns y\$latch 1 REG LCCOMB_X14_Y2_N28 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X14_Y2_N28; Fanout = 1; REG Node = 'y\$latch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { y$latch } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 26 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.518 ns) + CELL(1.972 ns) 2.490 ns y 2 PIN PIN_Y15 0 " "Info: 2: + IC(0.518 ns) + CELL(1.972 ns) = 2.490 ns; Loc. = PIN_Y15; Fanout = 0; PIN Node = 'y'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { y$latch y } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.972 ns ( 79.20 % ) " "Info: Total cell delay = 1.972 ns ( 79.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.518 ns ( 20.80 % ) " "Info: Total interconnect delay = 0.518 ns ( 20.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { y$latch y } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { y$latch {} y {} } { 0.000ns 0.518ns } { 0.000ns 1.972ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.118 ns" { clk q[1] Equal1~17 y$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.118 ns" { clk {} clk~combout {} q[1] {} Equal1~17 {} y$latch {} } { 0.000ns 0.000ns 1.046ns 1.083ns 0.981ns } { 0.000ns 0.840ns 0.712ns 0.228ns 0.228ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { y$latch y } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { y$latch {} y {} } { 0.000ns 0.518ns } { 0.000ns 1.972ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "xx x clk -2.405 ns register " "Info: th for register \"xx\" (data pin = \"x\", clock pin = \"clk\") is -2.405 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.504 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.504 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns clk 1 CLK PIN_W21 5 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_W21; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.046 ns) + CELL(0.618 ns) 2.504 ns xx 2 REG LCFF_X14_Y2_N9 1 " "Info: 2: + IC(1.046 ns) + CELL(0.618 ns) = 2.504 ns; Loc. = LCFF_X14_Y2_N9; Fanout = 1; REG Node = 'xx'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.664 ns" { clk xx } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.458 ns ( 58.23 % ) " "Info: Total cell delay = 1.458 ns ( 58.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.046 ns ( 41.77 % ) " "Info: Total interconnect delay = 1.046 ns ( 41.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.504 ns" { clk xx } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.504 ns" { clk {} clk~combout {} xx {} } { 0.000ns 0.000ns 1.046ns } { 0.000ns 0.840ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.058 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.058 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.830 ns) 0.830 ns x 1 PIN PIN_W19 1 " "Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_W19; Fanout = 1; PIN Node = 'x'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { x } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.919 ns) + CELL(0.309 ns) 5.058 ns xx 2 REG LCFF_X14_Y2_N9 1 " "Info: 2: + IC(3.919 ns) + CELL(0.309 ns) = 5.058 ns; Loc. = LCFF_X14_Y2_N9; Fanout = 1; REG Node = 'xx'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.228 ns" { x xx } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.139 ns ( 22.52 % ) " "Info: Total cell delay = 1.139 ns ( 22.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.919 ns ( 77.48 % ) " "Info: Total interconnect delay = 3.919 ns ( 77.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.058 ns" { x xx } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.058 ns" { x {} x~combout {} xx {} } { 0.000ns 0.000ns 3.919ns } { 0.000ns 0.830ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.504 ns" { clk xx } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.504 ns" { clk {} clk~combout {} xx {} } { 0.000ns 0.000ns 1.046ns } { 0.000ns 0.840ns 0.618ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.058 ns" { x xx } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.058 ns" { x {} x~combout {} xx {} } { 0.000ns 0.000ns 3.919ns } { 0.000ns 0.830ns 0.309ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}