fsk2.tan.qmsg

... ..应该有些用处.对于爱好EDA开发的人来说

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 6 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "6 " "Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "q\[2\] " "Info: Detected ripple clock \"q\[2\]\" as buffer" {  } { { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 19 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "q\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "q\[3\] " "Info: Detected ripple clock \"q\[3\]\" as buffer" {  } { { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 19 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "q\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "q\[1\] " "Info: Detected ripple clock \"q\[1\]\" as buffer" {  } { { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 19 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "q\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "q\[0\] " "Info: Detected ripple clock \"q\[0\]\" as buffer" {  } { { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 19 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "q\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Equal1~17 " "Info: Detected gated clock \"Equal1~17\" as buffer" {  } { { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 29 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "Equal1~17" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "xx " "Info: Detected ripple clock \"xx\" as buffer" {  } { { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 14 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "xx" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register m\[2\] register y\$latch 342.7 MHz 2.918 ns Internal " "Info: Clock \"clk\" has Internal fmax of 342.7 MHz between source register \"m\[2\]\" and destination register \"y\$latch\" (period= 2.918 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.255 ns + Longest register register " "Info: + Longest register to register delay is 0.255 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns m\[2\] 1 REG LCFF_X14_Y2_N31 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y2_N31; Fanout = 2; REG Node = 'm\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { m[2] } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.202 ns) + CELL(0.053 ns) 0.255 ns y\$latch 2 REG LCCOMB_X14_Y2_N28 1 " "Info: 2: + IC(0.202 ns) + CELL(0.053 ns) = 0.255 ns; Loc. = LCCOMB_X14_Y2_N28; Fanout = 1; REG Node = 'y\$latch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.255 ns" { m[2] y$latch } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 26 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.053 ns ( 20.78 % ) " "Info: Total cell delay = 0.053 ns ( 20.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.202 ns ( 79.22 % ) " "Info: Total interconnect delay = 0.202 ns ( 79.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.255 ns" { m[2] y$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.255 ns" { m[2] {} y$latch {} } { 0.000ns 0.202ns } { 0.000ns 0.053ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.440 ns - Smallest " "Info: - Smallest clock skew is -0.440 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 4.774 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 4.774 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns clk 1 CLK PIN_W21 5 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_W21; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.046 ns) + CELL(0.712 ns) 2.598 ns q\[2\] 2 REG LCFF_X14_Y2_N15 4 " "Info: 2: + IC(1.046 ns) + CELL(0.712 ns) = 2.598 ns; Loc. = LCFF_X14_Y2_N15; Fanout = 4; REG Node = 'q\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.758 ns" { clk q[2] } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.914 ns) + CELL(0.053 ns) 3.565 ns Equal1~17 3 COMB LCCOMB_X14_Y2_N24 4 " "Info: 3: + IC(0.914 ns) + CELL(0.053 ns) = 3.565 ns; Loc. = LCCOMB_X14_Y2_N24; Fanout = 4; COMB Node = 'Equal1~17'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.967 ns" { q[2] Equal1~17 } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.981 ns) + CELL(0.228 ns) 4.774 ns y\$latch 4 REG LCCOMB_X14_Y2_N28 1 " "Info: 4: + IC(0.981 ns) + CELL(0.228 ns) = 4.774 ns; Loc. = LCCOMB_X14_Y2_N28; Fanout = 1; REG Node = 'y\$latch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.209 ns" { Equal1~17 y$latch } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 26 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.833 ns ( 38.40 % ) " "Info: Total cell delay = 1.833 ns ( 38.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.941 ns ( 61.60 % ) " "Info: Total interconnect delay = 2.941 ns ( 61.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.774 ns" { clk q[2] Equal1~17 y$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.774 ns" { clk {} clk~combout {} q[2] {} Equal1~17 {} y$latch {} } { 0.000ns 0.000ns 1.046ns 0.914ns 0.981ns } { 0.000ns 0.840ns 0.712ns 0.053ns 0.228ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.214 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.214 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns clk 1 CLK PIN_W21 5 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_W21; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.046 ns) + CELL(0.712 ns) 2.598 ns xx 2 REG LCFF_X14_Y2_N9 1 " "Info: 2: + IC(1.046 ns) + CELL(0.712 ns) = 2.598 ns; Loc. = LCFF_X14_Y2_N9; Fanout = 1; REG Node = 'xx'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.758 ns" { clk xx } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.359 ns) + CELL(0.000 ns) 3.957 ns xx~clkctrl 3 COMB CLKCTRL_G6 3 " "Info: 3: + IC(1.359 ns) + CELL(0.000 ns) = 3.957 ns; Loc. = CLKCTRL_G6; Fanout = 3; COMB Node = 'xx~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.359 ns" { xx xx~clkctrl } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.639 ns) + CELL(0.618 ns) 5.214 ns m\[2\] 4 REG LCFF_X14_Y2_N31 2 " "Info: 4: + IC(0.639 ns) + CELL(0.618 ns) = 5.214 ns; Loc. = LCFF_X14_Y2_N31; Fanout = 2; REG Node = 'm\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.257 ns" { xx~clkctrl m[2] } "NODE_NAME" } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.170 ns ( 41.62 % ) " "Info: Total cell delay = 2.170 ns ( 41.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.044 ns ( 58.38 % ) " "Info: Total interconnect delay = 3.044 ns ( 58.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.214 ns" { clk xx xx~clkctrl m[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.214 ns" { clk {} clk~combout {} xx {} xx~clkctrl {} m[2] {} } { 0.000ns 0.000ns 1.046ns 1.359ns 0.639ns } { 0.000ns 0.840ns 0.712ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.774 ns" { clk q[2] Equal1~17 y$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.774 ns" { clk {} clk~combout {} q[2] {} Equal1~17 {} y$latch {} } { 0.000ns 0.000ns 1.046ns 0.914ns 0.981ns } { 0.000ns 0.840ns 0.712ns 0.053ns 0.228ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.214 ns" { clk xx xx~clkctrl m[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.214 ns" { clk {} clk~combout {} xx {} xx~clkctrl {} m[2] {} } { 0.000ns 0.000ns 1.046ns 1.359ns 0.639ns } { 0.000ns 0.840ns 0.712ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.670 ns + " "Info: + Micro setup delay of destination is 0.670 ns" {  } { { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 26 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 28 -1 0 } } { "fsk2.vhd" "" { Text "D:/文档/bishe/FSK解调程序/fsk2.vhd" 26 0 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.255 ns" { m[2] y$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.255 ns" { m[2] {} y$latch {} } { 0.000ns 0.202ns } { 0.000ns 0.053ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.774 ns" { clk q[2] Equal1~17 y$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.774 ns" { clk {} clk~combout {} q[2] {} Equal1~17 {} y$latch {} } { 0.000ns 0.000ns 1.046ns 0.914ns 0.981ns } { 0.000ns 0.840ns 0.712ns 0.053ns 0.228ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.214 ns" { clk xx xx~clkctrl m[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.214 ns" { clk {} clk~combout {} xx {} xx~clkctrl {} m[2] {} } { 0.000ns 0.000ns 1.046ns 1.359ns 0.639ns } { 0.000ns 0.840ns 0.712ns 0.000ns 0.618ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 12 " "Warning: Circuit may not operate. Detected 12 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}