fsk2.tan.rpt

... ..应该有些用处.对于爱好EDA开发的人来说

; N/A   ; None         ; 2.775 ns   ; start ; q[3] ; clk      ;
; N/A   ; None         ; 2.775 ns   ; start ; q[2] ; clk      ;
; N/A   ; None         ; 2.772 ns   ; start ; q[0] ; clk      ;
; N/A   ; None         ; 2.772 ns   ; start ; q[1] ; clk      ;
; N/A   ; None         ; 2.644 ns   ; x     ; xx   ; clk      ;
+-------+--------------+------------+-------+------+----------+


+---------------------------------------------------------------+
; tco                                                           ;
+-------+--------------+------------+---------+----+------------+
; Slack ; Required tco ; Actual tco ; From    ; To ; From Clock ;
+-------+--------------+------------+---------+----+------------+
; N/A   ; None         ; 7.608 ns   ; y$latch ; y  ; clk        ;
+-------+--------------+------------+---------+----+------------+


+-------------------------------------------------------------------+
; th                                                                ;
+---------------+-------------+-----------+-------+------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To   ; To Clock ;
+---------------+-------------+-----------+-------+------+----------+
; N/A           ; None        ; -2.405 ns ; x     ; xx   ; clk      ;
; N/A           ; None        ; -2.533 ns ; start ; q[0] ; clk      ;
; N/A           ; None        ; -2.533 ns ; start ; q[1] ; clk      ;
; N/A           ; None        ; -2.536 ns ; start ; q[3] ; clk      ;
; N/A           ; None        ; -2.536 ns ; start ; q[2] ; clk      ;
+---------------+-------------+-----------+-------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Wed Apr 16 12:30:31 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fsk2 -c fsk2 --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "y$latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "q[2]" as buffer
    Info: Detected ripple clock "q[3]" as buffer
    Info: Detected ripple clock "q[1]" as buffer
    Info: Detected ripple clock "q[0]" as buffer
    Info: Detected gated clock "Equal1~17" as buffer
    Info: Detected ripple clock "xx" as buffer
Info: Clock "clk" has Internal fmax of 342.7 MHz between source register "m[2]" and destination register "y$latch" (period= 2.918 ns)
    Info: + Longest register to register delay is 0.255 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y2_N31; Fanout = 2; REG Node = 'm[2]'
        Info: 2: + IC(0.202 ns) + CELL(0.053 ns) = 0.255 ns; Loc. = LCCOMB_X14_Y2_N28; Fanout = 1; REG Node = 'y$latch'
        Info: Total cell delay = 0.053 ns ( 20.78 % )
        Info: Total interconnect delay = 0.202 ns ( 79.22 % )
    Info: - Smallest clock skew is -0.440 ns
        Info: + Shortest clock path from clock "clk" to destination register is 4.774 ns
            Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_W21; Fanout = 5; CLK Node = 'clk'
            Info: 2: + IC(1.046 ns) + CELL(0.712 ns) = 2.598 ns; Loc. = LCFF_X14_Y2_N15; Fanout = 4; REG Node = 'q[2]'
            Info: 3: + IC(0.914 ns) + CELL(0.053 ns) = 3.565 ns; Loc. = LCCOMB_X14_Y2_N24; Fanout = 4; COMB Node = 'Equal1~17'
            Info: 4: + IC(0.981 ns) + CELL(0.228 ns) = 4.774 ns; Loc. = LCCOMB_X14_Y2_N28; Fanout = 1; REG Node = 'y$latch'
            Info: Total cell delay = 1.833 ns ( 38.40 % )
            Info: Total interconnect delay = 2.941 ns ( 61.60 % )
        Info: - Longest clock path from clock "clk" to source register is 5.214 ns
            Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_W21; Fanout = 5; CLK Node = 'clk'
            Info: 2: + IC(1.046 ns) + CELL(0.712 ns) = 2.598 ns; Loc. = LCFF_X14_Y2_N9; Fanout = 1; REG Node = 'xx'
            Info: 3: + IC(1.359 ns) + CELL(0.000 ns) = 3.957 ns; Loc. = CLKCTRL_G6; Fanout = 3; COMB Node = 'xx~clkctrl'
            Info: 4: + IC(0.639 ns) + CELL(0.618 ns) = 5.214 ns; Loc. = LCFF_X14_Y2_N31; Fanout = 2; REG Node = 'm[2]'
            Info: Total cell delay = 2.170 ns ( 41.62 % )
            Info: Total interconnect delay = 3.044 ns ( 58.38 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Micro setup delay of destination is 0.670 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Warning: Circuit may not operate. Detected 12 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "q[2]" and destination pin or register "m[2]" for clock "clk" (Hold time is 1.031 ns)
    Info: + Largest clock skew is 2.710 ns
        Info: + Longest clock path from clock "clk" to destination register is 5.214 ns
            Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_W21; Fanout = 5; CLK Node = 'clk'
            Info: 2: + IC(1.046 ns) + CELL(0.712 ns) = 2.598 ns; Loc. = LCFF_X14_Y2_N9; Fanout = 1; REG Node = 'xx'
            Info: 3: + IC(1.359 ns) + CELL(0.000 ns) = 3.957 ns; Loc. = CLKCTRL_G6; Fanout = 3; COMB Node = 'xx~clkctrl'
            Info: 4: + IC(0.639 ns) + CELL(0.618 ns) = 5.214 ns; Loc. = LCFF_X14_Y2_N31; Fanout = 2; REG Node = 'm[2]'
            Info: Total cell delay = 2.170 ns ( 41.62 % )
            Info: Total interconnect delay = 3.044 ns ( 58.38 % )
        Info: - Shortest clock path from clock "clk" to source register is 2.504 ns
            Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_W21; Fanout = 5; CLK Node = 'clk'
            Info: 2: + IC(1.046 ns) + CELL(0.618 ns) = 2.504 ns; Loc. = LCFF_X14_Y2_N15; Fanout = 4; REG Node = 'q[2]'
            Info: Total cell delay = 1.458 ns ( 58.23 % )
            Info: Total interconnect delay = 1.046 ns ( 41.77 % )
    Info: - Micro clock to output delay of source is 0.094 ns
    Info: - Shortest register to register delay is 1.734 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y2_N15; Fanout = 4; REG Node = 'q[2]'
        Info: 2: + IC(0.914 ns) + CELL(0.053 ns) = 0.967 ns; Loc. = LCCOMB_X14_Y2_N24; Fanout = 4; COMB Node = 'Equal1~17'
        Info: 3: + IC(0.266 ns) + CELL(0.346 ns) = 1.579 ns; Loc. = LCCOMB_X14_Y2_N30; Fanout = 1; COMB Node = 'm[2]~154'
        Info: 4: + IC(0.000 ns) + CELL(0.155 ns) = 1.734 ns; Loc. = LCFF_X14_Y2_N31; Fanout = 2; REG Node = 'm[2]'
        Info: Total cell delay = 0.554 ns ( 31.95 % )
        Info: Total interconnect delay = 1.180 ns ( 68.05 % )
    Info: + Micro hold delay of destination is 0.149 ns
Info: tsu for register "q[3]" (data pin = "start", clock pin = "clk") is 2.775 ns
    Info: + Longest pin to register delay is 5.189 ns
        Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_AB15; Fanout = 4; PIN Node = 'start'
        Info: 2: + IC(3.811 ns) + CELL(0.366 ns) = 5.034 ns; Loc. = LCCOMB_X14_Y2_N12; Fanout = 1; COMB Node = 'q~154'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.189 ns; Loc. = LCFF_X14_Y2_N13; Fanout = 4; REG Node = 'q[3]'
        Info: Total cell delay = 1.378 ns ( 26.56 % )
        Info: Total interconnect delay = 3.811 ns ( 73.44 % )
    Info: + Micro setup delay of destination is 0.090 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.504 ns
        Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_W21; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(1.046 ns) + CELL(0.618 ns) = 2.504 ns; Loc. = LCFF_X14_Y2_N13; Fanout = 4; REG Node = 'q[3]'
        Info: Total cell delay = 1.458 ns ( 58.23 % )
        Info: Total interconnect delay = 1.046 ns ( 41.77 % )
Info: tco from clock "clk" to destination pin "y" through register "y$latch" is 7.608 ns
    Info: + Longest clock path from clock "clk" to source register is 5.118 ns
        Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_W21; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(1.046 ns) + CELL(0.712 ns) = 2.598 ns; Loc. = LCFF_X14_Y2_N17; Fanout = 5; REG Node = 'q[1]'
        Info: 3: + IC(1.083 ns) + CELL(0.228 ns) = 3.909 ns; Loc. = LCCOMB_X14_Y2_N24; Fanout = 4; COMB Node = 'Equal1~17'
        Info: 4: + IC(0.981 ns) + CELL(0.228 ns) = 5.118 ns; Loc. = LCCOMB_X14_Y2_N28; Fanout = 1; REG Node = 'y$latch'
        Info: Total cell delay = 2.008 ns ( 39.23 % )
        Info: Total interconnect delay = 3.110 ns ( 60.77 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 2.490 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X14_Y2_N28; Fanout = 1; REG Node = 'y$latch'
        Info: 2: + IC(0.518 ns) + CELL(1.972 ns) = 2.490 ns; Loc. = PIN_Y15; Fanout = 0; PIN Node = 'y'
        Info: Total cell delay = 1.972 ns ( 79.20 % )
        Info: Total interconnect delay = 0.518 ns ( 20.80 % )
Info: th for register "xx" (data pin = "x", clock pin = "clk") is -2.405 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.504 ns
        Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_W21; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(1.046 ns) + CELL(0.618 ns) = 2.504 ns; Loc. = LCFF_X14_Y2_N9; Fanout = 1; REG Node = 'xx'
        Info: Total cell delay = 1.458 ns ( 58.23 % )
        Info: Total interconnect delay = 1.046 ns ( 41.77 % )
    Info: + Micro hold delay of destination is 0.149 ns
    Info: - Shortest pin to register delay is 5.058 ns
        Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_W19; Fanout = 1; PIN Node = 'x'
        Info: 2: + IC(3.919 ns) + CELL(0.309 ns) = 5.058 ns; Loc. = LCFF_X14_Y2_N9; Fanout = 1; REG Node = 'xx'
        Info: Total cell delay = 1.139 ns ( 22.52 % )
        Info: Total interconnect delay = 3.919 ns ( 77.48 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 5 warnings
    Info: Allocated 120 megabytes of memory during processing
    Info: Processing ended: Wed Apr 16 12:30:32 2008
    Info: Elapsed time: 00:00:01