cic1s2.syr

单级CIC2倍内插滤波器

Release 9.2.04i - xst J.40
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
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--> Reading design: cic1s2.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) Partition Resource Summary
     9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "cic1s2.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "cic1s2"
Output Format                      : NGC
Target Device                      : xcv100-5-bg256

---- Source Options
Top Module Name                    : cic1s2
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Convert Tristates To Logic         : Yes
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Library Search Order               : cic1s2.lso
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../cic1s2.v" in library work
Module <cic1s2> compiled
No errors in compilation
Analysis of file <"cic1s2.prj"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for module <cic1s2> in library <work> with parameters.
	sample = "00000000000000000000000000000001"
	zero = "00000000000000000000000000000000"


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <cic1s2>.
	sample = 32'sb00000000000000000000000000000001
	zero = 32'sb00000000000000000000000000000000
Module <cic1s2> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <cic1s2>.
    Related source file is "../cic1s2.v".
    Found 12-bit register for signal <data_out>.
    Found 4-bit up counter for signal <count>.
    Found 1-bit register for signal <state>.
    Summary:
	inferred   1 Counter(s).
	inferred  13 D-type flip-flop(s).
Unit <cic1s2> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                                             : 1
 4-bit up counter                                      : 1
# Registers                                            : 2
 1-bit register                                        : 1
 12-bit register                                       : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file 'v100.nph' in environment D:\Xilinx92i.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 1
 4-bit up counter                                      : 1
# Registers                                            : 13
 Flip-Flops                                            : 13

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <cic1s2> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block cic1s2, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 17
 Flip-Flops                                            : 17

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : cic1s2.ngr
Top Level Output File Name         : cic1s2
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 25

Cell Usage :
# BELS                             : 7
#      INV                         : 1
#      LUT2                        : 1
#      LUT3                        : 1
#      LUT4                        : 3
#      VCC                         : 1
# FlipFlops/Latches                : 17
#      FDE                         : 12
#      FDR                         : 5
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 24
#      IBUF                        : 12
#      OBUF                        : 12
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v100bg256-5 

 Number of Slices:                      10  out of   1200     0%  
 Number of Slice Flip Flops:            17  out of   2400     0%  
 Number of 4 input LUTs:                 6  out of   2400     0%  
 Number of IOs:                         25
 Number of bonded IOBs:                 25  out of    180    13%  
 Number of GCLKs:                        1  out of      4    25%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 17    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 6.014ns (Maximum Frequency: 166.279MHz)
   Minimum input arrival time before clock: 2.676ns
   Maximum output required time after clock: 7.511ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 6.014ns (frequency: 166.279MHz)
  Total number of paths / destination ports: 42 / 21
-------------------------------------------------------------------------
Delay:               6.014ns (Levels of Logic = 1)
  Source:            count_0 (FF)
  Destination:       count_0 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: count_0 to count_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              6   1.193   1.850  count_0 (count_0)
     LUT4:I0->O            4   0.642   1.600  count_cmp_eq00001 (count_cmp_eq0000)
     FDR:R                     0.729          count_0
    ----------------------------------------
    Total                      6.014ns (2.564ns logic, 3.450ns route)
                                       (42.6% logic, 57.4% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 12 / 12
-------------------------------------------------------------------------
Offset:              2.676ns (Levels of Logic = 1)
  Source:            data_in<0> (PAD)
  Destination:       data_out_0 (FF)
  Destination Clock: clk rising

  Data Path: data_in<0> to data_out_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.860   1.150  data_in_0_IBUF (data_in_0_IBUF)
     FDE:D                     0.666          data_out_0
    ----------------------------------------
    Total                      2.676ns (1.526ns logic, 1.150ns route)
                                       (57.0% logic, 43.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 12 / 12
-------------------------------------------------------------------------
Offset:              7.511ns (Levels of Logic = 1)
  Source:            data_out_11 (FF)
  Destination:       data_out<11> (PAD)
  Source Clock:      clk rising

  Data Path: data_out_11 to data_out<11>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              1   1.193   1.150  data_out_11 (data_out_11)
     OBUF:I->O                 5.168          data_out_11_OBUF (data_out<11>)
    ----------------------------------------
    Total                      7.511ns (6.361ns logic, 1.150ns route)
                                       (84.7% logic, 15.3% route)

=========================================================================
CPU : 3.94 / 4.53 s | Elapsed : 4.00 / 4.00 s
 
--> 

Total memory usage is 129532 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)