cic1s2_map.v

单级CIC2倍内插滤波器

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: J.40
//  \   \         Application: netgen
//  /   /         Filename: cic1s2_map.v
// /___/   /\     Timestamp: Sun Apr 13 15:13:49 2008
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -intstyle ise -s 5 -pcf cic1s2.pcf -sdf_anno true -sdf_path netgen/map -insert_glbl true -w -dir netgen/map -ofmt verilog -sim cic1s2_map.ncd cic1s2_map.v 
// Device	: v100bg256-5 (FINAL 1.124 2007-04-13)
// Input file	: cic1s2_map.ncd
// Output file	: D:\zym\cic1s2\netgen\map\cic1s2_map.v
// # of Modules	: 1
// Design Name	: cic1s2
// Xilinx        : D:\Xilinx92i
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Development System Reference Guide, Chapter 23
//     Synthesis and Simulation Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module cic1s2 (
  clk, clk2, data_out, data_in
);
  input clk;
  output clk2;
  output [11 : 0] data_out;
  input [7 : 0] data_in;
  wire state_0;
  wire clk_BUFGP;
  wire GLOBAL_LOGIC0;
  wire count_cmp_eq0000;
  wire state_not0001_0;
  wire \data_out<10>/OUTMUX_1 ;
  wire \data_out<11>/OUTMUX_2 ;
  wire \data_out<0>/OUTMUX_3 ;
  wire \data_out<1>/OUTMUX_4 ;
  wire \data_out<2>/OUTMUX_5 ;
  wire \data_out<3>/OUTMUX_6 ;
  wire \data_out<4>/OUTMUX_7 ;
  wire \data_out<5>/OUTMUX_8 ;
  wire \data_out<6>/OUTMUX_9 ;
  wire \data_out<7>/OUTMUX_10 ;
  wire \data_out<8>/OUTMUX_11 ;
  wire \clk2/OUTMUX_12 ;
  wire \data_out<9>/OUTMUX_13 ;
  wire \i0<2>/LOGIC_ONE_14 ;
  wire Mshreg_i0_2;
  wire \count<0>/BXMUXNOT ;
  wire count_cmp_eq0000_pack_1;
  wire \state/LOGIC_ZERO_15 ;
  wire \state/GROM ;
  wire state_not0001;
  wire VCC;
  wire GND;
  wire [2 : 2] i0;
  wire [1 : 0] count;
  wire [1 : 1] Result;
  initial $sdf_annotate("netgen/map/cic1s2_map.sdf");
  X_OPAD \data_out<10>/PAD  (
    .PAD(data_out[10])
  );
  X_OBUF data_out_10_OBUF (
    .I(\data_out<10>/OUTMUX_1 ),
    .O(data_out[10])
  );
  X_BUF \data_out<10>/OUTMUX  (
    .I(i0[2]),
    .O(\data_out<10>/OUTMUX_1 )
  );
  X_OPAD \data_out<11>/PAD  (
    .PAD(data_out[11])
  );
  X_OBUF data_out_11_OBUF (
    .I(\data_out<11>/OUTMUX_2 ),
    .O(data_out[11])
  );
  X_BUF \data_out<11>/OUTMUX  (
    .I(i0[2]),
    .O(\data_out<11>/OUTMUX_2 )
  );
  X_OPAD \data_out<0>/PAD  (
    .PAD(data_out[0])
  );
  X_OBUF data_out_0_OBUF (
    .I(\data_out<0>/OUTMUX_3 ),
    .O(data_out[0])
  );
  X_BUF \data_out<0>/OUTMUX  (
    .I(i0[2]),
    .O(\data_out<0>/OUTMUX_3 )
  );
  X_OPAD \data_out<1>/PAD  (
    .PAD(data_out[1])
  );
  X_OBUF data_out_1_OBUF (
    .I(\data_out<1>/OUTMUX_4 ),
    .O(data_out[1])
  );
  X_BUF \data_out<1>/OUTMUX  (
    .I(i0[2]),
    .O(\data_out<1>/OUTMUX_4 )
  );
  X_OPAD \data_out<2>/PAD  (
    .PAD(data_out[2])
  );
  X_OBUF data_out_2_OBUF (
    .I(\data_out<2>/OUTMUX_5 ),
    .O(data_out[2])
  );
  X_BUF \data_out<2>/OUTMUX  (
    .I(i0[2]),
    .O(\data_out<2>/OUTMUX_5 )
  );
  X_OPAD \data_out<3>/PAD  (
    .PAD(data_out[3])
  );
  X_OBUF data_out_3_OBUF (
    .I(\data_out<3>/OUTMUX_6 ),
    .O(data_out[3])
  );
  X_BUF \data_out<3>/OUTMUX  (
    .I(i0[2]),
    .O(\data_out<3>/OUTMUX_6 )
  );
  X_OPAD \data_out<4>/PAD  (
    .PAD(data_out[4])
  );
  X_OBUF data_out_4_OBUF (
    .I(\data_out<4>/OUTMUX_7 ),
    .O(data_out[4])
  );
  X_BUF \data_out<4>/OUTMUX  (
    .I(i0[2]),
    .O(\data_out<4>/OUTMUX_7 )
  );
  X_OPAD \data_out<5>/PAD  (
    .PAD(data_out[5])
  );
  X_OBUF data_out_5_OBUF (
    .I(\data_out<5>/OUTMUX_8 ),
    .O(data_out[5])
  );
  X_BUF \data_out<5>/OUTMUX  (
    .I(i0[2]),
    .O(\data_out<5>/OUTMUX_8 )
  );
  X_OPAD \data_out<6>/PAD  (
    .PAD(data_out[6])
  );
  X_OBUF data_out_6_OBUF (
    .I(\data_out<6>/OUTMUX_9 ),
    .O(data_out[6])
  );
  X_BUF \data_out<6>/OUTMUX  (
    .I(i0[2]),
    .O(\data_out<6>/OUTMUX_9 )
  );
  X_OPAD \data_out<7>/PAD  (
    .PAD(data_out[7])
  );
  X_OBUF data_out_7_OBUF (
    .I(\data_out<7>/OUTMUX_10 ),
    .O(data_out[7])
  );
  X_BUF \data_out<7>/OUTMUX  (
    .I(i0[2]),
    .O(\data_out<7>/OUTMUX_10 )
  );
  X_OPAD \data_out<8>/PAD  (
    .PAD(data_out[8])
  );
  X_OBUF data_out_8_OBUF (
    .I(\data_out<8>/OUTMUX_11 ),
    .O(data_out[8])
  );
  X_BUF \data_out<8>/OUTMUX  (
    .I(i0[2]),
    .O(\data_out<8>/OUTMUX_11 )
  );
  X_OPAD \clk2/PAD  (
    .PAD(clk2)
  );
  X_OBUF clk2_OBUF (
    .I(\clk2/OUTMUX_12 ),
    .O(clk2)
  );
  X_BUF \clk2/OUTMUX  (
    .I(state_0),
    .O(\clk2/OUTMUX_12 )
  );
  X_OPAD \data_out<9>/PAD  (
    .PAD(data_out[9])
  );
  X_OBUF data_out_9_OBUF (
    .I(\data_out<9>/OUTMUX_13 ),
    .O(data_out[9])
  );
  X_BUF \data_out<9>/OUTMUX  (
    .I(i0[2]),
    .O(\data_out<9>/OUTMUX_13 )
  );
  X_ONE \i0<2>/LOGIC_ONE  (
    .O(\i0<2>/LOGIC_ONE_14 )
  );
  defparam \Mshreg_i0_2/SRL16E .INIT = 16'h0000;
  X_SRL16E \Mshreg_i0_2/SRL16E  (
    .A0(GLOBAL_LOGIC0),
    .A1(GLOBAL_LOGIC0),
    .A2(GLOBAL_LOGIC0),
    .A3(GLOBAL_LOGIC0),
    .D(i0[2]),
    .CE(\i0<2>/LOGIC_ONE_14 ),
    .CLK(clk_BUFGP),
    .Q(Mshreg_i0_2)
  );
  defparam i0_2.INIT = 1'b0;
  X_FF i0_2 (
    .I(Mshreg_i0_2),
    .CE(VCC),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(GND),
    .O(i0[2])
  );
  defparam count_cmp_eq00001.INIT = 16'h2222;
  X_LUT4 count_cmp_eq00001 (
    .ADR0(count[0]),
    .ADR1(count[1]),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(count_cmp_eq0000_pack_1)
  );
  defparam \Mcount_count_xor<1>11 .INIT = 16'h6666;
  X_LUT4 \Mcount_count_xor<1>11  (
    .ADR0(count[1]),
    .ADR1(count[0]),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(Result[1])
  );
  X_INV \count<0>/BXMUX  (
    .I(count[0]),
    .O(\count<0>/BXMUXNOT )
  );
  X_BUF \count<0>/XUSED  (
    .I(count_cmp_eq0000_pack_1),
    .O(count_cmp_eq0000)
  );
  defparam count_1.INIT = 1'b0;
  X_SFF count_1 (
    .I(Result[1]),
    .CE(VCC),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(GND),
    .SSET(GND),
    .SRST(count_cmp_eq0000),
    .O(count[1])
  );
  X_ZERO \state/LOGIC_ZERO  (
    .O(\state/LOGIC_ZERO_15 )
  );
  defparam \state/G .INIT = 16'hFFFF;
  X_LUT4 \state/G  (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\state/GROM )
  );
  defparam state.INIT = 1'b1;
  X_SFF state (
    .I(\state/GROM ),
    .CE(VCC),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(GND),
    .SSET(\state/LOGIC_ZERO_15 ),
    .SRST(state_not0001_0),
    .O(state_0)
  );
  defparam state_not00011.INIT = 16'hDDDD;
  X_LUT4 state_not00011 (
    .ADR0(count[0]),
    .ADR1(count[1]),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(state_not0001)
  );
  X_BUF \state_not0001/YUSED  (
    .I(state_not0001),
    .O(state_not0001_0)
  );
  defparam count_0.INIT = 1'b0;
  X_SFF count_0 (
    .I(\count<0>/BXMUXNOT ),
    .CE(VCC),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(GND),
    .SSET(GND),
    .SRST(count_cmp_eq0000),
    .O(count[0])
  );
  X_ZERO GLOBAL_LOGIC0_GND (
    .O(GLOBAL_LOGIC0)
  );
  X_IPAD \clk/PAD  (
    .PAD(clk)
  );
  X_CKBUF \clk_BUFGP/BUFG/BUF  (
    .I(clk),
    .O(clk_BUFGP)
  );
  X_ONE NlwBlock_cic1s2_VCC (
    .O(VCC)
  );
  X_ZERO NlwBlock_cic1s2_GND (
    .O(GND)
  );
endmodule


`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

    wire GSR;
    wire GTS;
    wire PRLD;

    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule