cic1s2t.v

来自「单级CIC2倍内插滤波器」· Verilog 代码 · 共 72 行

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:11:45 04/13/2008
// Design Name:   cic1s2
// Module Name:   D:/zym/cic1s2/cic1s2t.v
// Project Name:  cic1s2
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: cic1s2
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module cic1s2t_v;

	// Inputs
	reg clk;
	reg [11:0] data_in;
	//outputs
	wire [11:0]data_out;

	// Instantiate the Unit Under Test (UUT)
	cic1s2 uut (
		.clk(clk), 
		.data_in(data_in), 
		.data_out(data_out)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		data_in = 0;
		//clk2 = 0;
		//data_out = 0;

		// Wait 100 ns for global reset to finish
		#100;
      //forever #10 clk = !clk; 
		// Add stimulus here
	end
		
		always
			begin
				#10 clk=~clk;
			end
			
		always
			begin
			#100 data_in<=12'h01;
			#100 data_in<=12'h02;
			#100 data_in<=12'h03;
			#100 data_in<=12'h04;
			#100 data_in<=12'h05;
			#100 data_in<=12'h06;			
			end
      
endmodule