cic3s2.v

来自「单级CIC2倍内插滤波器」· Verilog 代码 · 共 77 行

module cic1s2(clk,data_in,clk2,data_out)

input clk;
input [7:0] data_in;
output clk2;
output [11:0] data_out;

reg clk2;
parameter sample=1,zero=0;

reg state;
reg [1:0] count;
reg [7:0] data
reg [11:0] c0,c0_pre,i0,i0_pre;

initial 
   begin
       count<=0;
       c0<=0;
       c0_pre<=0;
       c1<=0;
       c1_pre<=0;
       state<=sample;
   end
 
 assign data_out=i0;
 assign sxtdata={{4{data[7]}},data};
 
 always@(posedge clk)
    begin: FSM
     if(count==1)
        begin
            count<=0;
            state<=sample;
            clk2<=1;
        end
    else
       begin
        count<=count+1;
        state<=zero;
        clk2<=0;
       end
    end

always@(posedge clk)
   begin : Int
      if(state==sample)
         begin
             i<=c;
             i0=i+i0_pre;
             i0_pre=i0;
         end
       else
          begin
              i<=0;
              i0=i+i0_pre;
             i0_pre=i0;
         end
         $display("i0=%h",i0);
   end
   
   always@(posedge clk)
      begin:Comb
         if(state==sample)
            begin
                data<=data_in;
                c0=stxdata;
                c=c0-c0_pre;
                c0_pre=c0;
            end
        $display("c0=%h",c0);
      end