memcfg.h

2410 NOR FLASH的 BSP

/* configNet.h - network configuration header */

/* Copyright 1999-2000 Wind River Systems, Inc. */
/* Copyright 1999-2000 ARM Limited */

/*
modification history
--------------------
01e,16jul02,m_h  C++ protection
01d,20nov00,jpd  reworked endDevTbl definitions to be dynamically filled in.
01c,07feb00,jpd  updated copyright message.
01b,13jan00,pr   added DEC entry.
01a,10nov99,ajb  Copied from pid7t version 01c.
*/



#ifndef __memcfg_H__
#define __memcfg_H__

#ifdef __cplusplus
extern "C" {
#endif

/*BWSCON*/
#define		DW8			(0x0)
#define		DW16			(0x1)
#define		DW32			(0x2)
#define		WAIT			(0x1<<2)
#define		UBLB			(0x1<<3)

/*bus width*/
#define		B1_BWSCON		(DW16)
#define		B2_BWSCON		(DW16)
#define		B3_BWSCON		(DW16)
#define		B4_BWSCON		(DW8)
#define		B5_BWSCON		(DW16)
#define		B6_BWSCON		(DW32)
#define		B7_BWSCON		(DW32)

#define         B1_WS                   (0)
#define         B2_WS                   (0)
#define         B3_WS                   (1)
#define         B4_WS                   (0)
#define         B5_WS                   (0)
#define         B6_WS                   (0)
#define         B7_WS                   (0)

#define         B1_ST                   (0)
#define         B2_ST                   (0)
#define         B3_ST                   (1)
#define         B4_ST                   (0)
#define         B5_ST                   (0)
#define         B6_ST                   (0)
#define         B7_ST                   (0)

/*BANK0CON*/
#define		B0_Tacs			0x0	/*0clk*/
#define		B0_Tcos			0x0	/*0clk*/
#define		B0_Tacc			0x7	/*14clk*/
#define		B0_Tcoh			0x0	/*0clk*/
#define		B0_Tah			0x0	/*0clk*/
#define		B0_Tacp			0x0	
#define		B0_PMC			0x0	/*normal*/

/*BANK1CON*/
#define		B1_Tacs			0x0	/*0clk*/
#define		B1_Tcos			0x0	/*0clk*/
#define		B1_Tacc			0x7	/*14clk*/
#define		B1_Tcoh			0x0	/*0clk*/
#define		B1_Tah			0x0	/*0clk*/
#define		B1_Tacp			0x0	
#define		B1_PMC			0x0	/*normal*/

/*Bank 2 parameter*/
#define		B2_Tacs			0x0	/*0clk*/
#define		B2_Tcos			0x0	/*0clk*/
#define		B2_Tacc			0x7	/*14clk*/
#define		B2_Tcoh			0x0	/*0clk*/
#define		B2_Tah			0x0	/*0clk*/
#define		B2_Tacp			0x0	
#define		B2_PMC			0x0	/*normal*/

/*Bank 3 parameter*/
#define		B3_Tacs			0x1	/*0clk*/
#define		B3_Tcos			0x1	/*0clk*/
#define		B3_Tacc			0x7	/*14clk*/
#define		B3_Tcoh			0x0	/*0clk*/
#define		B3_Tah			0x0	/*0clk*/
#define		B3_Tacp			0x0	
#define		B3_PMC			0x0	/*normal*/

/*Bank 4 parameter*/
#define		B4_Tacs			0x3	/*0clk*/
#define		B4_Tcos			0x3	/*0clk*/
#define		B4_Tacc			0x7	/*14clk*/
#define		B4_Tcoh			0x3	/*0clk*/
#define		B4_Tah			0x3	/*0clk*/
#define		B4_Tacp			0x0	
#define		B4_PMC			0x0	/*normal*/

/*Bank 5 parameter*/
#define		B5_Tacs			0x0	/*0clk*/
#define		B5_Tcos			0x0	/*0clk*/
#define		B5_Tacc			0x7	/*14clk*/
#define		B5_Tcoh			0x0	/*0clk*/
#define		B5_Tah			0x0	/*0clk*/
#define		B5_Tacp			0x0	
#define		B5_PMC			0x0	/*normal*/

/*Bank 6 parameter*/
#define		B6_MT			0x3	/*SDRAM*/
/*B6_Trcd			0x0	*//*2clk*/
#define		B6_Trcd			0x1	/*3clk*/
#define		B6_SCAN			0x1	/*9bit*/

/*Bank 7 parameter*/
#define		B7_MT			0x3	/*SDRAM*/
/*B7_Trcd			0x0	*//*2clk*/
#define		B7_Trcd			0x1	/*3clk*/
#define		B7_SCAN			0x1	/*9bit*/

/*REFRESH parameter*/
#define		REFEN			0x1	/*Refresh enable*/
#define		TREFMD			0x0	/*CBR(CAS before RAS)/Auto refresh*/
#define		Trp			0x0	/*2clk*/
#define		Trc			0x3	/*7clk*/
		
#define		Tchr			0x2	/*3clk*/
#define		REFCNT			1113	/*period=15.6us, HCLK=60Mhz, (2048+1-15.6*60)*/
/*value*/
#define		valBWSCON	 	(0+(B1_BWSCON<<4)+(B1_WS<<6)+(B1_ST<<7)+(B2_BWSCON<<8)+(B2_WS<<10)+(B2_ST<<11)+(B3_BWSCON<<12)+(B3_WS<<14)+(B3_ST<<15)+(B4_BWSCON<<16)+(B4_WS<<18)+(B4_ST<<19)+(B5_BWSCON<<20)+(B5_WS<<22)+(B5_ST<<23)+(B6_BWSCON<<24)+(B6_WS<<26)+(B6_ST<<27)+(B7_BWSCON<<28)+(B7_WS<<30)+(B7_ST<<31))
#define		valBANKCON0	 	((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))   /*GCS0*/
#define		valBANKCON1	    	((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))   /*GCS1 */
#define		valBANKCON2	    	((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))   /*GCS2*/
#define		valBANKCON3	    	((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))   /*GCS3*/
#define		valBANKCON4	    	((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))   /*GCS4*/
#define		valBANKCON5    	 	((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))   /*GCS5*/
#define		valBANKCON6    	 	((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))    /*GCS6*/
#define		valBANKCON7    	 	((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))    /*GCS7*/
#define		valREFRESH    	 	((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)    
#define		valBANKSIZE	 	0x32            /*SCLK power saving mode, BANKSIZE 128M/128M*/
#define		valMRSBR6	 	0x30            /*MRSR6 CL=3clk*/
#define		valMRSBR7    	 	0x30            /*MRSR7*/

#define		SDRAM_TOP_ADDR		0x34000000
#define		LOCKOUT  	        0xC0  /*IRQ FIQ disable*/
#define  	MMU_NWI           	0x00  /*非buffer 非catch*/
#define		MMU_BUF           	0x04  /*buufer*/
#define		MMU_CATCH         	0x08  /*catch*/
#define		MMU_WI            	0x0c  /*catch*/
#ifdef __cplusplus
}
#endif
#endif