rominit.s

2410 BSP vxworks xia下

/* romInit.s - ARM Integrator ROM initialization module */

/* Copyright 1999-2001 ARM Limited */
/* Copyright 1999-2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01m,25jan02,m_h  sdata needs "_" for bootrom_res
01l,09oct01,jpd  added clock speed setting for 946ES.
01k,03oct01,jpd  tidied slightly.
01j,28sep01,pr   added support for ARM946ES.
01i,04jun01,rec  memory clock rate changes for 740t
01h,21feb01,h_k  added support for ARM966ES and ARM966ES_T.
01g,20nov00,jpd  change speeds on 920T and add conditional early
		 enabling of I-cache on 920T.
01f,18sep00,rec  Add delay during power up
01e,23feb00,jpd  comments changes.
01d,22feb00,jpd  changed copyright string.
01c,20jan00,jpd  added support for ARM720T/ARM920T.
01b,13jan00,pr	 added support for ARM740T.
01a,30nov99,ajb  created, based on PID version 01i.
*/

/*
DESCRIPTION
This module contains the entry code for VxWorks images that start
running from ROM, such as 'bootrom' and 'vxWorks_rom'.  The entry
point, romInit(), is the first code executed on power-up.  It performs
the minimal setup needed to call the generic C routine romStart() with
parameter BOOT_COLD.

romInit() masks interrupts in the processor and the interrupt
controller and sets the initial stack pointer (to STACK_ADRS which is
defined in configAll.h).  Other hardware and device initialisation is
performed later in the sysHwInit routine in sysLib.c.

The routine sysToMonitor() jumps to a location after the beginning of
romInit, (defined by ROM_WARM_ADRS) to perform a "warm boot".  This
entry point allows a parameter to be passed to romStart().

The routines in this module don't use the "C" frame pointer %r11@ ! or
establish a stack frame.

SEE ALSO:
.I "ARM Architecture Reference Manual,"
.I "ARM 7TDMI Data Sheet,"
.
 "ARM 720T Data Sheet,"
.I "ARM 740T Data Sheet,"
.I "ARM 920T Technical Reference Manual",
.I "ARM 940T Technical Reference Manual",
.I "ARM 946E-S Technical Reference Manual",
.I "ARM 966E-S Technical Reference Manual",
.I "ARM Reference Peripherals Specification,"
.I "ARM Integrator/AP User Guide",
.I "ARM Integrator/CM7TDMI User Guide",
.I "ARM Integrator/CM720T User Guide",
.I "ARM Integrator/CM740T User Guide",
.I "ARM Integrator/CM920T User Guide",
.I "ARM Integrator/CM940T User Guide",
.I "ARM Integrator/CM946E User Guide",
.I "ARM Integrator/CM9x6ES Datasheet".
*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "asm.h"
#include "regs.h"	
#include "config.h"
#include "integrator.h"
#include "arch/arm/mmuArmLib.h"
#include "memcfg.h"     /*SDRAM config register*/
	.data
        .globl   VAR(copyright_wind_river)
        .long    VAR(copyright_wind_river)

/* internals */

	.globl	FUNC(romInit)		/* start of system code */
	.globl	VAR(sdata)		/* start of data */
        .globl  _sdata
	.globl	VAR(integratorMemSize)	/* actual memory size */


/* externals */

	.extern	FUNC(romStart)	/* system initialization routine */

_sdata:
VAR_LABEL(sdata)
	.asciz	"start of data"
	.balign	4

/* variables */

	.data

VAR_LABEL(integratorMemSize)
	.long	0

	.text
	.balign 4

/*******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*

* romInit
*     (
*     int startType	/@ only used by 2nd entry point @/
*     )

* INTERNAL
* sysToMonitor examines the ROM for the first instruction and the string
* "Copy" in the third word so if this changes, sysToMonitor must be updated.
*/

_ARM_FUNCTION(romInit)
_romInit:
cold:
	MOV	r0, #BOOT_COLD	/* fall through to warm boot entry */
warm:
	B	start

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii   "Copyright 1999-2001 ARM Limited"
	.ascii   "\nCopyright 1999-2001 Wind River Systems, Inc."
	.balign 4

start:
	/*
	 * There have been reports of problems with certain boards and
	 * certain power supplies not coming up after a power-on reset,
	 * and adding a delay at the start of romInit appears to help
	 * with this.
	 */
	TEQS	r0, #BOOT_COLD
	MOVEQ	r1, #INTEGRATOR_DELAY_VALUE
	MOVNE	r1, #1
	
	ldr    r2,=0x40000000	/*internal sram,just store r0*/
	str    r0,[r2]


delay_loop:
	SUBS	r1, r1, #1
	BNE	delay_loop
	
	


	/* Setup MMU Control Register */

	MOV	r1, #MMU_INIT_VALUE		/* Defined in mmuArmLib.h */
	ORR	r1, r1, #MMUCR_I_ENABLE		/* enable Icache*/
	MCR	CP_MMU, 0, r1, c1, c0, 0	/* Write to MMU CR */

	MOV	r1, #0				/* data SBZ */
	MCR	CP_MMU, 0, r1, c7, c10, 4	/* drain write-buffer */
	MCR	CP_MMU, 0, r1, c7, c7, 0	/* R1 = 0 from above, data SBZ*/

	/* disable interrupts in CPU and switch to SVC32 mode */

	MRS	r1, cpsr
	BIC	r1, r1, #MASK_MODE
	ORR	r1, r1, #MODE_SVC32 | I_BIT | F_BIT
	MSR	cpsr, r1

/***************************************************************************************/
	/*add by yang tian chi*/
	ldr   r0,L$_WTCON         /*disable watch dog*/
    	ldr   r1,=0x0
    	str   r1,[r0]

	ldr   r0,L$_INTMSK        /*all interrupt disable(if  r1=0x00000000 all interrupt service)*/
    	ldr   r1,=0xffffffff
    	str   r1,[r0]

	ldr   r0,L$_INTSUBMSK     /*all subinterrupt disable*/
    	ldr   r1,=0x7ff            /*(only ten subinterrupt are valid in 2410 from low end*/
    	str   r1,[r0]              /*so r1= 0x7ff)*/
    	
    	/*turn on the led,and make it glitter*/
    	ldr   r0,L$_GPFCON        /*config the I/O of port F*/
    	ldr   r1,=0x5500
    	str   r1,[r0]
	
	ldr   r0,=GPFUP
	ldr   r1,=0xffffffff
	ldr   r1,[r0]
	
	ldr   r0,=0x00
	ldr   r1,L$_GPFDAT
	str   r0,[r1]

	/*config PLL,now FCLK=30MHz*/
	ldr   r0,L$_MPLLCON	   
	ldr   r1,L$_FCLKCFG
	str   r1,[r0]              
	
	/*SDRAM init,BANKx init*/
	/*only 13 registers need to be init*/
	ldr   r0 ,L$_valSMRDATA	   /*SDRAM config value*/
	ldr   r1 ,L$_valSMRDATA + 0x04
	ldr   r2 ,L$_valSMRDATA + 0x08
	ldr   r3 ,L$_valSMRDATA + 0x0C
	ldr   r4 ,L$_valSMRDATA + 0x10
	ldr   r5 ,L$_valSMRDATA + 0x14
	ldr   r6 ,L$_valSMRDATA + 0x18
	ldr   r7 ,L$_valSMRDATA + 0x1C
	ldr   r8 ,L$_valSMRDATA + 0x20
	ldr   r9 ,L$_valSMRDATA + 0x24
	ldr   r10,L$_valSMRDATA + 0x28
	ldr   r11,L$_valSMRDATA + 0x2C
	ldr   r12,L$_valSMRDATA + 0x30
    	ldr   r13,L$_BWSCON
    	stmia r13,{r0-r12}        
 	
   	/*ok SDRAM and BANKx are also initialised*/
   	
    	/* program copy*/
	ldr	r0, =RESET_ROM_START
	/*ldr	r1, =0x100000*/			/*L$_RomCopySize,4*0x100000=0x400000*/
	ldr	r1, L$_RomCopySize
	ldr	r2, =RESET_DRAM_START        	/* Copy DRAM area base */

ROM2SDRAM_COPY_LOOP:
    	LDR    r3, [r0], #4
    	STR    r3, [r2], #4
    	SUBS   r1, r1, #4         		/* Down Count */
    	BNE    ROM2SDRAM_COPY_LOOP
    	
/*
**MMU
*/
    	add	r1, pc, #MMU_Table - (. + 8)
    	/*ldr     r1,=MMU_Table*/
    	ldr     r0,=SDRAM_TOP_ADDR 		/*SDRAM TOP ADDRESS*/
        sub     r0,r0,#0x100000    		/*most top of 1M space reserved*/

	mov     r10,r0
    	mov     r7 ,r0
    	mov     r11,r1
    	
    	mov	r0, #0x02		    
	orr	r0, r0, #0x400		    /*enable r/w*/
MMU1:
	mov	r1, r11			     

        
MMU2:
	ldr	r2, [r1], #4		    /* (r2) = virtual address to map Bank at*/
	ldr	r3, [r1], #4		    /* (r3) = physical address to map from*/
	ldr	r4, [r1], #4		    /* (r4) = num MB to map  */
	ldr     r5, [r1], #4                /* (r5) = C/B*/

	cmp	r4, #0                      /* last item is all zero*/
	beq	MMU4

/*        orr	r0, r0, r5                  *//* 添加C/B方式控制位*/

	ldr	r6, =0xFFF00000
	and	r2, r2, r6             

	and	r3, r3, r6              /* PA needs 4GB, 1MB aligned.*/

	add	r2, r10, r2, LSR #18    
                                        
	add	r0, r0, r3              /* (r0) = PTE for next physical page*/
                                        

MMU3:
	str	r0, [r2], #4            
	add	r0, r0, #0x00100000     /* (r0) = PTE for next physical page*/
	                            	
	sub	r4, r4, #1              /* Decrement number of MB left */
	cmp	r4, #0
	bne	MMU3                    /* Map next MB*/
    
    bic	r0, r0, #0xF0000000     	/* Clear Section Base Address Field*/
	bic	r0, r0, #0x0FF00000     /* Clear Section Base Address Field*/
    bic	r0, r0, #0xc                /* Clear Section Base Address Field*/
    b	MMU2                    	/* Get next element*/
MMU4:
       mov	r10, r7		/* (r10) = restore address of 1st level page table*/


/* The page tables and exception vectors are setup. Initialize the MMU and turn
 it on.
*/
  	mov     r1, #1
  	MCR	CP_MMU, 0, r1,  c3, c0, 0                  /* setup access to domain 0*/
	MCR	CP_MMU, 0, r10, c2, c0, 0
	ldr     r1, =0x107d             /* Enable: MMU*/

	cmp     r0, #0                  /* make sure no stall on "mov pc,r0" below*/
	MCR	CP_MMU, 0, r1, c1, c0, 0       /* enable the MMU & Caches*/
	
	nop
	nop

/*	
*  sys timer and aux timer init
*/	
	
	ldr	r0,=0x51000004	/*TCFG1*/
	ldr	r1,=0xfff00fff
	str	r1,[r0]
	
	ldr	r0,=0x51000000  /*TCFG0*/
	ldr	r1,=0xe00
	str	r1,[r0]
	
	ldr	r0,=0x5100003c  /*TCNTB4*/
	ldr	r1,=20000
	str	r1,[r0]
	
	ldr	r0,=0x5100003c  /*TCON*/
	ldr	r1,=0x600000
	str	r1,[r0]
	
	ldr	r0,=0x5100003c  /*TCON*/
	ldr	r1,=0x500000
	str	r1,[r0]
	
	ldr	r0,=0x51000030  /*TCNTB3*/
	ldr	r1,=1000
	str	r1,[r0]
	
	ldr	r0,=0x5100003c  /*TCON*/
	ldr	r1,=0x5A0000
	str	r1,[r0]
	
	ldr	r0,=0x5100003c  /*TCON*/
	ldr	r1,=0x590000
	str	r1,[r0]
	

	/*The interrupt and sub interrupt,watchdog are disable,sdram and other bankx are
	also init at this point.*/ 
	/*add end*/
/***************************************************************************************/

	/*
	 * Jump to the normal (higher) ROM Position. After a reset, the
	 * ROM is mapped into memory from* location zero upwards as well
	 * as in its normal position at This code could be executing in
	 * the lower position. We wish to be executing the code, still
	 * in ROM, but in its normal (higher) position before we remap
	 * the machine so that the ROM is no longer dual-mapped from zero
	 * upwards, but so that RAM appears from 0 upwards.
	 */

	LDR	pc, L$_HiPosn
HiPosn:
	
	ldr    r5,=0x40000000
	ldr    r0, [r5]        /* restore starttype to r0 from r13 */
	LDR	sp, L$_STACK_ADDR
	MOV	fp, #0			/* zero frame pointer */

	/* jump to C entry point in ROM: routine - entry point + ROM base */

	LDR	pc, L$_rStrtInRom
/******************************************************************************/

/*
 * PC-relative-addressable pointers - LDR Rn,=sym is broken
 * note "_" after "$" to stop preprocessor performing substitution
 */

	.balign	4

L$_HiPosn:
	.long	ROM_TEXT_ADRS + HiPosn - FUNC(romInit)

L$_rStrtInRom:
	.long	ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)

L$_STACK_ADDR:
	.long	STACK_ADRS

L$_memSize:
	.long	VAR(integratorMemSize)

/*S3C2410X internal register ,add by yang tian chi,define in 2410addr.h*/
L$_WTCON:
	.long   WTCON		/*watchdog control */
L$_INTMSK:
	.long   INTMSK		/*int mask register*/
L$_INTSUBMSK:
	.long	INTSUBMSK	/*sub interrupt mask register*/
L$_GPFCON:
	.long	GPFCON		/*port F config register*/
L$_GPFDAT:
	.long	GPFDAT		/*port F data register*/
L$_BWSCON:
	.long	BWSCON		/*mem cfg register base address*/
L$_FCLKCFG:
	.long	FCLKCFG		/*FCLK config value*/
L$_MPLLCON:
	.long	MPLLCON	/*PLL config parameter register*/
L$_valSMRDATA:
	.long	valBWSCON
	.long	valBANKCON0
	.long	valBANKCON1
	.long	valBANKCON2
	.long	valBANKCON3
	.long	valBANKCON4
	.long	valBANKCON5
	.long	valBANKCON6
	.long	valBANKCON7
	.long	valREFRESH
	.long	valBANKSIZE
	.long	valMRSBR6
	.long	valMRSBR7
L$_RomCopySize:
    .long    L$_RomCopySize - FUNC(romInit)
MMU_Table:
/*L$_MMU_Table:*/
    /*    vir add      phy add    size     C/B	*/
    .long 0x40000000, 0x40000000,  1   ,  0xc    
    .long 0x08000000, 0x08000000, 32   ,  0X0/* 32 MB SROM(SRAM/ROM) BANK 1*/
    .long 0x84000000, 0x10000000, 32   ,  0X0/* 32 MB SROM(SRAM/ROM) BANK 2*/
    .long 0x18000000, 0x18000000, 32   ,  0X0/* 32 MB SROM(SRAM/ROM) BANK 3*/
    .long 0x20000000, 0x20000000, 32   ,  0X0/* 32 MB SROM(SRAM/ROM) BANK 4*/
    .long 0x28000000, 0x28000000, 32   ,  0X0/* 32 MB SROM(SRAM/ROM) BANK 5*/
    .long 0x00000000, 0x30000000, 63   ,  0X0/* 32 MB DRAM BANK 0*/
    .long 0x33F00000, 0x33F00000,  1   ,  0X0/* 32 MB DRAM BANK 0*/
    .long 0x48000000, 0x48000000,  1   ,  0X0/* Memory control register*/
    .long 0x49000000, 0x49000000,  1   ,  0X0/* USB Host register*/
    .long 0x4A000000, 0x4A000000,  1   ,  0X0/* Interrupt Control register*/
    .long 0x4B000000, 0x4B000000,  1   ,  0X0/* DMA control register*/
    .long 0x4C000000, 0x4C000000,  1   ,  0X0/* Clock & Power register*/
    .long 0x4D000000, 0x4D000000,  1   ,  0X0/* LCD control register*/
    .long 0x4E000000, 0x4E000000,  1   ,  0X0/* NAND flash control register*/
    .long 0x50000000, 0x50000000,  1   ,  0X0/* UART control register*/
    .long 0x51000000, 0x51000000,  1   ,  0X0/* PWM timer register*/
    .long 0x52000000, 0x52000000,  1   ,  0X0/* USB device register*/
    .long 0x53000000, 0x53000000,  1   ,  0X0/* Watchdog Timer register*/
    .long 0x54000000, 0x54000000,  1   ,  0X0/* IIC control register*/
    .long 0x55000000, 0x55000000,  1   ,  0X0/* IIS control register*/
    .long 0x56000000, 0x56000000,  1   ,  0X0/* I/O Port register*/
    .long 0x57000000, 0x57000000,  1   ,  0X0/* RTC control register*/
    .long 0x58000000, 0x58000000,  1   ,  0X0/* A/D convert register*/
    .long 0x59000000, 0x59000000,  1   ,  0X0/* SPI register*/
    .long 0x5A000000, 0x5A000000,  1   ,  0X0/* SD Interface register*/
    .long 0x24000000, 0x00000000, 16   ,  0X0/* 32 MB SROM(SRAM/ROM) BANK 0*/
    .long 0x00000000, 0x00000000,  0   ,  0X0/* End of Table (MB MUST BE ZERO!)*/

/*add end*/

#if defined(CPU_940T) || defined (CPU_940T_T)

L$_sysCacheUncachedAdrs:
	.long	SYS_CACHE_UNCACHED_ADRS
L$_SDRAM_TOP_ADDR:
	.long	SDRAM_TOP_ADDR
#endif /* defined(CPU_940T, CPU_940T_T) */