📄 fmd.cpp
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// Initialize ECC register
NF_RSTECC();
// Enable Chip
NF_CE_L();
// Issue command
NF_CMD(CMD_READ);
NF_CMD(CMD_WRITE);
// Setup address
NF_ADDR(0x00);
NF_ADDR((startSectorAddr) & 0xff);
NF_ADDR((startSectorAddr >> 8) & 0xff);
if (NEED_EXT_ADDR) {
NF_ADDR((startSectorAddr >> 16) & 0xff);
}
// Special case to handle un-aligned buffer pointer.
//
if( ((DWORD) pSectorBuff) & 0x3) {
// Write the data
for(i=0; i<SECTOR_SIZE; i++) {
NF_DATA_W(pSectorBuff[i]);
}
}
else {
WritePage512(pSectorBuff, pNFDATA);
}
// Read out the ECC value generated by HW
dwECCVal = NF_ECC();
// Write the SectorInfo data to the media
// NOTE: This hardware is odd: only a byte can be written at a time and it must reside in the
// upper byte of a USHORT.
if(pSectorInfoBuff)
{
// Write the first reserved field (DWORD)
NF_DATA_W( (pSectorInfoBuff->dwReserved1 >> 24) & 0xff );
NF_DATA_W( (pSectorInfoBuff->dwReserved1 >> 16) & 0xff );
NF_DATA_W( (pSectorInfoBuff->dwReserved1 >> 8 ) & 0xff );
NF_DATA_W( (pSectorInfoBuff->dwReserved1) & 0xff );
// Write OEM reserved flag
NF_DATA_W( (pSectorInfoBuff->bOEMReserved) );
// Write the bad block flag
NF_DATA_W( (pSectorInfoBuff->bBadBlock) );
// Write the second reserved field
NF_DATA_W( (pSectorInfoBuff->wReserved2 >> 8) & 0xff );
NF_DATA_W( (pSectorInfoBuff->wReserved2) & 0xff );
}else
{
// Make sure we advance the Flash's write pointer (even though we aren't writing the SectorInfo data)
for(i=0; i<sizeof(SectorInfo); i++)
{
NF_DATA_W(0xff);
}
}
// ECC stuff should be here
eccBuf[0] = (BYTE) ((dwECCVal) & 0xff);
eccBuf[1] = (BYTE) ((dwECCVal >> 8) & 0xff);
eccBuf[2] = (BYTE) ((dwECCVal >> 16) & 0xff);
// Write the ECC value to the flash
for(i=0; i<3; i++) {
NF_DATA_W(eccBuf[i]);
}
// Finish up the write operation
NF_CMD(CMD_WRITE2);
// Wait for RB
NF_WAITRB();
// Check the status
NF_CMD(CMD_STATUS);
if(NF_DATA_R() & STATUS_ERROR) {
#ifdef BOOT_LOADER
EdbgOutputDebugString("FMD_WriteSector() ######## Error Programming page %d!\r\n", startSectorAddr);
#else
RETAILMSG(1, (TEXT("FMD_WriteSector() ######## Error Programming page %d!\n"), startSectorAddr));
#endif
bRet = FALSE;
}
// Disable the chip
NF_CE_H();
RELEASEMUTEX();
return bRet;
}
/*
* MarkBlockBad
*
* Mark the block as a bad block. We need to write a 00 to the 517th byte
*/
BOOL MarkBlockBad(BLOCK_ID blockID)
{
DWORD dwStartPage = blockID << 5;
BOOL bRet = TRUE;
GRABMUTEX();
// Enable chip
NF_CE_L();
// Issue command
// We are dealing with spare area
NF_CMD(CMD_READ2);
NF_CMD(CMD_WRITE);
// Set up address
NF_ADDR(VALIDADDR);
NF_ADDR((dwStartPage) & 0xff);
NF_ADDR((dwStartPage >> 8) & 0xff);
if (NEED_EXT_ADDR) {
NF_ADDR((dwStartPage >> 16) & 0xff);
}
NF_DATA_W(BADBLOCKMARK);
// Copmlete the write
NF_CMD(CMD_WRITE2);
// Wait for RB
NF_WAITRB();
// Get the status
NF_CMD(CMD_STATUS);
if(NF_DATA_R() & STATUS_ERROR) {
RETAILMSG(1, (TEXT("######## Failed to mark the block bad!\n")));
bRet = FALSE;
}
// Disable chip select
NF_CE_H();
RELEASEMUTEX();
return bRet;
}
//
// FMD_SetBlockStatus
//
// Sets the status of a block. Only implement for bad blocks for now.
// Returns TRUE if no errors in setting.
//
BOOL FMD_SetBlockStatus(BLOCK_ID blockID, DWORD dwStatus)
{
SECTOR_ADDR sectorAddr = blockID << LOG_2_PAGES_PER_BLOCK;
BYTE bStatus = 0;
if(dwStatus & BLOCK_STATUS_BAD)
{
if(!MarkBlockBad (blockID))
{
return FALSE;
}
}
// We don't currently support setting a block to read-only, so fail if request is
// for read-only and block is not currently read-only.
if(dwStatus & BLOCK_STATUS_READONLY)
{
if(!(FMD_GetBlockStatus(blockID) & BLOCK_STATUS_READONLY))
{
return FALSE;
}
}
return TRUE;
}
#ifndef NOSYSCALL
// We don't have to build the following interface functions for the
// bootloader.
//
// FMD_PowerUp
//
// Performs any necessary powerup procedures...
//
VOID FMD_PowerUp(VOID)
{
if (v_s2410CLKPWR && pNFCONF) {
// Enable the clock to NAND controller
v_s2410CLKPWR->rCLKCON |= (1<<4);
// Reinit the NAND controller
GRABMUTEX();
WRITE_REGISTER_USHORT(pNFCONF, NFCONF_INIT);
RELEASEMUTEX();
// Reset the controller
NF_Reset();
#ifdef CEDAR_ONLY
// ++ CE 3.0 Specific Code. Not needed for 4.x +
SetInterruptEvent(SYSINTR_POWERON);
// -- CE 3.0 Specific Code. Not needed for 4.x +
#endif // CEDAR_ONLY
}
}
// FMD_PowerDown
//
// Performs any necessary powerdown procedures...
//
VOID FMD_PowerDown(VOID)
{
if (v_s2410CLKPWR) {
// Disable the clock to NAND controller
v_s2410CLKPWR->rCLKCON &= ~(1<<4);
}
}
// FMD_OEMIoControl
//
// Used for any OEM defined IOCTL operations
//
BOOL FMD_OEMIoControl(DWORD dwIoControlCode, PBYTE pInBuf, DWORD nInBufSize,
PBYTE pOutBuf, DWORD nOutBufSize, PDWORD pBytesReturned)
{
switch(dwIoControlCode)
{
case IOCTL_FMD_UPDATEXIP_BEGIN:
g_bTakeMutex = TRUE;
break;
case IOCTL_FMD_UPDATEXIP_END:
g_bTakeMutex = FALSE;
break;
default:
RETAILMSG(1, (TEXT("FMD::FMD_OEMIoControl = 0x%x\n"), dwIoControlCode));
return FALSE;
}
return TRUE;
}
#endif // NOSYSCALL
//------------------------------- Private Interface (NOT used by the FAL) --------------------------
// FMD_GetOEMReservedByte
//
// Retrieves the OEM reserved byte (for metadata) for the specified physical sector.
//
//
BOOL FMD_GetOEMReservedByte(SECTOR_ADDR physicalSectorAddr, PBYTE pOEMReserved)
{
GRABMUTEX();
// Enable chip select
NF_CE_L();
// Issue command
NF_CMD(CMD_READ2);
// Set up address
NF_ADDR(OEMADDR);
NF_ADDR((physicalSectorAddr) & 0xff);
NF_ADDR((physicalSectorAddr >> 8) & 0xff);
if (NEED_EXT_ADDR) {
NF_ADDR((physicalSectorAddr >> 16) & 0xff);
}
// Wait for the ready bit
NF_WAITRB();
// Read the data
*pOEMReserved = (BYTE) NF_DATA_R();
// Disable chip select
NF_CE_H();
RELEASEMUTEX();
return TRUE;
}
// FMD_SetOEMReservedByte
//
// Sets the OEM reserved byte (for metadata) for the specified physical sector.
//
BOOL FMD_SetOEMReservedByte(SECTOR_ADDR physicalSectorAddr, BYTE bOEMReserved)
{
BOOL bRet = TRUE;
GRABMUTEX();
// Enable chip select
NF_CE_L();
// Issue command
NF_CMD(CMD_READ2);
NF_CMD(CMD_WRITE);
// Set up address
NF_ADDR(OEMADDR);
NF_ADDR((physicalSectorAddr) & 0xff);
NF_ADDR((physicalSectorAddr >> 8) & 0xff);
if (NEED_EXT_ADDR) {
NF_ADDR((physicalSectorAddr >> 16) & 0xff);
}
// Write the data
NF_DATA_W(bOEMReserved);
// Complete the write
NF_CMD(CMD_WRITE2);
// Wait for the ready bit
NF_WAITRB();
// Read the status
NF_CMD(CMD_STATUS);
// Check the status
if(NF_DATA_R() & STATUS_ERROR) {
RETAILMSG(1, (TEXT("######## Failed to set OEM Reserved byte!\n")));
bRet = FALSE;
}
// Disable chip select
NF_CE_H();
RELEASEMUTEX();
return bRet;
}
//---------------------------------------- Helper Functions ----------------------------------------
// Interface function for testing purpose.
//
BOOL FMD_ReadSpare(DWORD dwStartPage, LPBYTE pBuff, DWORD dwNumPages)
{
DWORD i, n;
GRABMUTEX();
// Enable chip select
NF_CE_L();
// Issue command
NF_CMD(CMD_READ2);
// Set up address
NF_ADDR(0x00);
NF_ADDR((dwStartPage) & 0xff);
NF_ADDR((dwStartPage >> 8) & 0xff);
if (NEED_EXT_ADDR) {
NF_ADDR((dwStartPage >> 16) & 0xff);
}
// Wait for Ready bit
NF_WAITRB();
// Now read out the data
for(n=0; n<dwNumPages; n++) {
// Read the spare area
for(i=0; i<16; i++) {
pBuff[n*16+i] = (BYTE) NF_DATA_R();
}
NF_WAITRB();
}
NF_CE_H();
RELEASEMUTEX();
return TRUE;
}
void GRABMUTEX()
{
#ifdef NOSYSCALL
#ifndef BOOT_LOADER
// we're in the kernel - always SC_WaitForMultiple
SC_WaitForMultiple(1, &g_hMutex, TRUE, INFINITE);
#endif
#else
if (g_bTakeMutex) {
// we can do a normal WaitForSingleObject
WaitForSingleObject(g_hMutex, INFINITE);
}
#endif
}
void RELEASEMUTEX()
{
#ifdef NOSYSCALL
#ifndef BOOT_LOADER
SC_ReleaseMutex(g_hMutex);
#endif
#else
if (g_bTakeMutex) {
ReleaseMutex(g_hMutex);
}
#endif
}
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