dram.cc
来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· CC 代码 · 共 1,471 行 · 第 1/5 页
CC
1,471 行
/*fprintf(stderr,"%4d \n",lat);debugging*/ if (overlap <= 0) /*memory interface is not busy*/ { if (memctrlpipe_enable == true) { busy_until[current_bank]=curTick+lat+ timing_correction; } else { if (busy_until[current_bank] >= curTick) { busy_until[current_bank]+=(lat+ timing_correction); total_arb_latency += (busy_until[current_bank] - curTick - lat - timing_correction); lat=busy_until[current_bank] - curTick; } else busy_until[current_bank]=curTick+lat+ timing_correction; } } else/*the memory request will be satisfied temp cycles after curTick*/ { busy_until[current_bank] +=(lat+ timing_correction); command_overlapping++; lat+=overlap; total_arb_latency += overlap; } // DR for power stats if( was_miss ) { cycles_between_misses[0] += (busy_until[current_bank] - time_last_miss); time_last_miss = busy_until[current_bank]; } // cout <<"cpu id = " << _cpu_num << "current_bank = " << current_bank << endl; // if((_cpu_num < num_cpus) && (_cpu_num >= 0)) // bank_access_profile[_cpu_num][current_bank]++; return lat; } /***********************************************************/ /******************** DRDRAM ***********************/ /***********************************************************/ else if ((mem_type == "DRDRAM") && (mem_actpolicy == "open"))/*DRDRAM*/ /*a closed bank has an activ_row number of DR_NUM_ROWS: highest +1*/ { if ((memctrladdr_type != "interleaved"))/* i.e. mc_type is linear */ { current_bank=physic_address/DR_BANK_SIZE; temp=physic_address-current_bank*DR_BANK_SIZE;/*address in bank*/ current_row=temp/DR_ROW_SIZE; current_device=current_bank/(DR_NUM_BANKS/DR_NUM_DEVS); } else/*mc_type interleaved*/ /* This memory controller maps the addresses differently * depending on the row-size, every row is mapped to another * bank. So the text segment uses half of every bank. The heap * the next quarter of each bank and the stack the rest. */ { num_blocks = physic_address/DR_ROW_SIZE; /* row number */ current_bank=(num_blocks%DR_NUM_BANKS)*2; /*every 'second' bank will be used*/ /*banks above DR_NUM_BANKS are the uneven banks*/ current_bank = ((current_bank < DR_NUM_BANKS) ? current_bank:(current_bank - DR_NUM_BANKS+1)); current_row=num_blocks/DR_NUM_BANKS; current_device=current_bank/(DR_NUM_BANKS/DR_NUM_DEVS); } if (abs(current_bank-last_bank)==1)/*access to an adjacent bank*/ { if (!((current_bank%DR_BANK_SAMP == (DR_BANK_SAMP-1))&&(last_bank%DR_BANK_SAMP == 0))/*not 15/16 (current/last)*/ &&(!((last_bank%DR_BANK_SAMP == (DR_BANK_SAMP-1))&&(current_bank%DR_BANK_SAMP == 0))))/*not 16/15(current/last)*/ { adjacent_access++; adjacent=1;/*an adjacent bank is accessed*/ if (cmdIsRead) adjacent_read++; else adjacent_write++; } } precharge=0;/*at this moment no bank needs to be precharged*/ if (active_row[current_bank] == DR_NUM_ROWS)/*bank is precharged*/ { if (prechargeBanksAround(current_bank)> 0)/*a bank next to the current is activated*/ { if ((adjacent==1)&&(precharge==1)) { /*since adjacent banks share SAMPs, this access would be the same as (in terms of latency) *an access to another row in the same bank if only one adjacent bank was active*/ last_bank = current_bank; last_row = current_row+1; precharge=0;/*set to 0 for next memory access*/ } } } if (mem_access_details == true) { //fprintf(mem_accessfd," %09u %4d %3d %15d\n",physic_address,current_row,current_bank,(int)adjacent_access); } else { if (mem_access_output!=NULL) { //fprintf(mem_accessfd,"\n"); } } total_access++; if (memctrlpipe_enable == true) { overlap=(int)(busy_until[current_bank] - curTick); } else overlap=0; if (cpu_ratio < 1.0) { corrected_overlap = overlap*((int)(1/cpu_ratio)); /* floor */ } else { corrected_overlap = (int) (overlap/cpu_ratio); } /*fprintf(stderr,"%10.0f %10.0f %6d %6d %2d %2d ",(double)busy_until, (double)curTick, overlap, corrected_overlap,precharge,adjacent);debugging*/ if (cmdIsRead == lastCmdIsRead)/*same command*/ { if (current_bank == last_bank)/*same bank*/ { if (current_row == last_row)/*same row*/ { if (cmdIsRead) { if (corrected_overlap > 0)/*overlapping*/ { /*best case*/ if (corrected_overlap >= DR_T_READ_READ_SROW) { lat=DR_BEST_T_READ_READ_SROW; srow_flag = true; best_case++; full_overlapping++; } else/*in between case*/ { lat = DR_T_READ_READ_SROW-corrected_overlap; srow_flag = true; in_between_case++; partial_overlapping++; } } else { /*worst case*/ lat = DR_T_READ_READ_SROW; srow_flag = true; worst_case++; } same_row_read_access++; srr_after_read++; } else/*write, always retire the previous data*/ { if (corrected_overlap > 0)/*overlapping*/ { /*best case*/ if (corrected_overlap >= DR_T_OWR) { lat=DR_BEST_T_WRITE_WRITE_SROW; srow_flag = true; best_case++; full_overlapping++; } else/*in between case*/ { lat = DR_T_WRITE_WRITE_SROW-corrected_overlap; srow_flag = true; in_between_case++; partial_overlapping++; } } else { /*worst case*/ lat = DR_T_WRITE_WRITE_SROW; srow_flag = true; worst_case++; } same_row_write_access++; srw_after_write++; } } else /*other row in same bank*/ { if (cmdIsRead) { if (corrected_overlap > 0)/*overlapping*/ { if (corrected_overlap >= DR_T_HELP)/*best case*/ { lat = DR_BEST_T_READ_READ_SBANK; best_case++; full_overlapping++; } else/*in between case*/ { lat = DR_T_READ_READ_SBANK-corrected_overlap; in_between_case++; partial_overlapping++; } } else/*worst case*/ { lat = DR_T_READ_READ_SBANK; worst_case++; } same_bank_read_access++; sbr_after_read++; } else/*write*/ { if (corrected_overlap > 0)/*overlapping*/ { if (corrected_overlap >= DR_T_OWR)/*best case*/ { lat = DR_BEST_T_WRITE_WRITE_SBANK; best_case++; full_overlapping++; } else/*in between case*/ { lat = DR_T_WRITE_WRITE_SBANK-corrected_overlap; in_between_case++; partial_overlapping++; } } else/*worst case*/ { lat = DR_T_WRITE_WRITE_SBANK; worst_case++; } same_bank_write_access++; sbw_after_write++; } } } else /*other bank*/ { if (cmdIsRead) { if (current_row == active_row[current_bank])/*row is still active*/ { if (corrected_overlap > 0 )/*overlapping*/ { if(corrected_overlap >= (DR_T_CAC+DR_T_PACKET))/*best case*/ { lat = DR_BEST_T_READ_READ_OBANK; best_case++; full_overlapping++; } else/*in between case*/ { lat = DR_T_CAC+DR_T_PACKET-corrected_overlap; in_between_case++; partial_overlapping++; } } else/*in between case*/ { lat = DR_T_CAC+DR_T_PACKET; in_between_case++; } other_bank_read_access_hit++; obr_after_read_hit++; } else/*row is not active or bank is precharged/not active*/ { if (active_row[current_bank]!=DR_NUM_ROWS)/*row is not active, but bank is active*/ { if (corrected_overlap > 0 )/*overlapping*/ { if(corrected_overlap >= (DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET))/*best case*/ { lat = DR_BEST_T_READ_READ_OBANK; best_case++; full_overlapping++; }
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