dram.cc

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· CC 代码 · 共 1,471 行 · 第 1/5 页

/*
 * Copyright (c) 2004
 * The Regents of The University of Michigan
 * All Rights Reserved
 *
 * This code is part of the M5 simulator.
 *
 * Permission is granted to use, copy, create derivative works and
 * redistribute this software and such derivative works for any
 * purpose, so long as the copyright notice above, this grant of
 * permission, and the disclaimer below appear in all copies made; and
 * so long as the name of The University of Michigan is not used in
 * any advertising or publicity pertaining to the use or distribution
 * of this software without specific, written prior authorization.
 *
 * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
 * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
 * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
 * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
 * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
 * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
 * DAMAGES.
 *
 * Authors: Ali G. Saidi
 *          Ronald G. Dreslinski Jr
 */

/*
 Copyright (c) 2000 Computer Engineering and Communication Networks Lab (TIK)
 Swiss Federal Institute of Technology (ETH) Zurich, Switzerland

 All rights reserved.
 Permission is hereby granted, without written agreement and without
 license or royalty fees, to use, copy, modify, and distribute this
 software and its documentation for any purpose, provided that the above
 copyright notice and the following two paragraphs appear in all copies
 of this software.

 IN NO EVENT SHALL THE TIK OR THE ETH ZURICH BE LIABLE TO ANY PARTY
 FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
 ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
 THE TIK OR THE ETH ZURICH HAVE BEEN ADVISED OF THE POSSIBILITY OF
 SUCH DAMAGE.

 THE TIK AND THE ETH ZURICH SPECIFICALLY DISCLAIM ANY WARRANTIES,
 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE
 PROVIDED HEREUNDER IS ON AN "AS IS" BASIS, AND TIK AND THE ETH ZURICH
 HAVE NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES,
 ENHANCEMENTS, OR MODIFICATIONS.
*/

/* authors: Andreas Romer 4/99 - 7/99
            Matthias Gries 4/99 - 2/01


References: http://www.tik.ee.ethz.ch/
======================================
-> Publications http://www.tik.ee.ethz.ch/db/tik/publications/form_search_publications.php3


Matthias Gries: A Survey of Synchronous RAM Architectures.
TIK Report Nr. 71, Computer Engineering and Networks Lab (TIK),
Swiss Federal Institute of Technology (ETH) Zurich, April, 1999

-> DRAM survey


Matthias Gries, Andreas Romer: Performance Evaluation of Recent
DRAM Architectures for Embedded Systems.
TIK Report Nr. 82, Computer Engineering and Networks Lab (TIK),
Swiss Federal Institute of Technology (ETH) Zurich, November, 1999.

-> description of the DRAM and controller models for SimpleScalar in the appendix
(note that the current software version additionally supports overlapping in
 closed-page mode with slightly modified timing)


Matthias Gries: The Impact of Recent DRAM Architectures on Embedded Systems Performance.
Euromicro2000, Symposium on Digital Systems Design, IEEE Computer, Maastricht, Netherlands,
Vol. 1, pages 282-289, September, 2000.

-> performance study with SimpleScalar


Matthias Gries: Modeling a Memory Subsystem with Petri Nets: a Case Study.
A. Yakovlev, L. Gomes, and L. Lavagno (Eds), Hardware Design and Petri Nets,
Kluwer Academic, pages 291-310, March, 2000.

-> SDRAM + controller performance model as a high-level Petri net
*/

/**
 * @file
 * Definition of a DRAM like main memory.
 */

#include <cstdlib>
#include <string>

#include "mem/dram.hh"

extern int maxThreadsPerCPU;

/* SDRAM system: PC100/PC133 2-2-2 DIMM timing according to
   PC SDRAM Specification, Rev. 1.7, Intel Corp, Nov. 1999.

   64 bit DIMM consists of four 16x organized 256 Mbit SDRAMs, 128 MByte of main memory in total.*/
/* the settings above must be changed if another memory is used */
/* DRDRAM system: 16 bit channel, four chips (single RIMM), 128 MByte of main memory in total.
   Timing: Rambus Inc, Direct RDRAM, preliminary information, 256/288Mbit: 40-800 timing */


#define  DR_STACK_BASE 0x8000000 /* total size of memory: 128 Mbyte */
#define  DR_BANK_SIZE  0x100000  /* size of a bank      :   1 Mbyte */
#define  DR_ROW_SIZE 0x800       /* size of a row       :   2 Kbyte */
#define  DR_NUM_BANKS (DR_STACK_BASE/DR_BANK_SIZE)      /* number of banks        : 128 */
#define  DR_NUM_ROWS (DR_BANK_SIZE/DR_ROW_SIZE)         /* number of rows per bank: 512 */
#define  DR_DATA_BASE  0x4000000 /* Size of textsegment :  64 Mbyte */
#define  DR_NUM_BYTE_MEM  16     /* data packet capacity:  16 byte  */
#define  DR_NUM_DEVS 4   /* number of devices along channel */
#define  DR_BANK_SAMP 16 /* 16 banks are together in one group in each device: bank 15 and 16 have no shared SAMPs */
#define  DR_T_PACKET 4   /* number of cycles (in 400 MHz) the memory needs to deliver a data packet */
#define  DR_T_RCD 7  /* RAS to CAS delay */
#define  DR_T_CAC 8  /* read access delay: number of cylces from read to data  (trailing to leading edge of packet!) */
#define  DR_T_CWD 6  /* Write delay: number of cylces from write to write data (trailing to leading edge of packet!) */
#define  DR_T_RP  8  /* row precharge delay */
#define  DR_T_RTR 8  /* retire delay*/
#define  DR_T_RDP 4  /* min delay from read to precharge in cycles */
#define  DR_T_PP  8  /* precharge to precharge time to any bank in the same device */
#define  DR_T_RAS 20 /* minimal row active time */
/*the settings above need to be changed if the memory is altered*/
#define  DR_DYNAMIC_SIZE (DR_STACK_BASE - DR_DATA_BASE) /* size of the heap and stack at most: 64 Mbyte */
// #define  DR_NUM_BANKS (DR_STACK_BASE/DR_BANK_SIZE)      /* number of banks        : 128 */
// #define  DR_NUM_ROWS (DR_BANK_SIZE/DR_ROW_SIZE)         /* number of rows per bank: 512 */
#define  DR_T_OWR (DR_T_CWD + DR_T_PACKET - DR_T_RTR)   /* overlap after write retire   */
#define  DR_T_HELP (DR_T_CAC+DR_T_PACKET-DR_T_RDP+DR_T_PACKET) /* used for read after read with precharge */
/*delays until data is ready/written to the memory for the DRDRAM*/
#define  DR_T_READ_READ_SROW    (DR_T_CAC + DR_T_PACKET) /* RAR, row hit, current bank */
#define  DR_T_READ_WRITE_SROW   (DR_T_CAC + DR_T_PACKET) /* RAW, row hit, current bank */
#define  DR_T_WRITE_READ_SROW   (DR_T_CWD + DR_T_PACKET) /* WAR, row hit, current bank */
#define  DR_T_WRITE_WRITE_SROW  (DR_T_CWD + DR_T_PACKET) /* WAW, row hit, current bank */
#define  DR_T_READ_READ_SBANK   (DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET) /* RAR, row miss, current bank */
#define  DR_T_READ_WRITE_SBANK  (DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET) /* RAW, row miss, current bank */
#define  DR_T_WRITE_READ_SBANK  (DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET) /* WAR, row miss, current bank */
#define  DR_T_WRITE_WRITE_SBANK (DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET) /* WAR, row miss, current bank */
#define  DR_T_READ_READ_OBANK   (DR_T_PP+DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET) /* RAR, row miss, another bank */
#define  DR_T_READ_WRITE_OBANK  (DR_T_PP+DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET) /* RAW, row miss, another bank */
#define  DR_T_WRITE_READ_OBANK  (DR_T_PP+DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET) /* WAR, row miss, another bank */
#define  DR_T_WRITE_WRITE_OBANK (DR_T_PP+DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET) /* WAR, row miss, another bank */
/* best-case latencies (due to overlap / row hits in another bank) */
#define  DR_BEST_T_READ_READ_SROW    0                               /* RAR, row hit, current bank */
#define  DR_BEST_T_READ_WRITE_SROW   (DR_T_CAC+DR_T_PACKET-DR_T_OWR) /* RAW, row hit, current bank */
#define  DR_BEST_T_WRITE_READ_SROW   0                               /* WAR, row hit, current bank */
#define  DR_BEST_T_WRITE_WRITE_SROW  (DR_T_CWD+DR_T_PACKET-DR_T_OWR) /* WAR, row hit, current bank */
#define  DR_BEST_T_READ_READ_SBANK   (DR_T_RCD + DR_T_CAC)                            /* RAR, row miss, current bank */
#define  DR_BEST_T_READ_WRITE_SBANK  (DR_T_RP-DR_T_OWR+DR_T_RCD+DR_T_CAC+DR_T_PACKET) /* RAW, row miss, current bank */
#define  DR_BEST_T_WRITE_READ_SBANK  (DR_T_RCD+DR_T_CWD)                              /* WAR, row miss, current bank */
#define  DR_BEST_T_WRITE_WRITE_SBANK (DR_T_RP-DR_T_OWR+DR_T_RCD+DR_T_CWD+DR_T_PACKET) /* WAW, row miss, current bank */
#define  DR_BEST_T_READ_READ_OBANK   0                   /* RAR, row miss/hit, another bank   */
#define  DR_BEST_T_READ_WRITE_OBANK  (DR_T_PACKET+DR_T_CAC-DR_T_OWR) /* RAW, row miss/hit, another bank */
#define  DR_BEST_T_WRITE_READ_OBANK  0                   /* WAR, row miss/hit, another bank   */
#define  DR_BEST_T_WRITE_WRITE_OBANK 0                   /* WAW, row miss/hit, another bank   */
#define  DR_BEST_T_READ_WRITE_ODEV   (DR_T_CAC-DR_T_CWD) /* RAW, row miss/hit, another device */


#define MIN(a,b) ((a<b) ? a : b)
#define  SD_ROW_SIZE 0x1000      /* size of a row       :   4 Kbyte */



DRAMMemory::DRAMMemory(const Params *p)
    : PhysicalMemory(p), cpu_ratio(p->cpu_ratio), bus_width(p->bus_width),
      mem_type(p->mem_type), mem_actpolicy(p->mem_actpolicy),
      memctrladdr_type(p->memctrladdr_type), act_lat(p->act_lat),
      cas_lat(p->cas_lat), war_lat(p->war_lat),
      pre_lat(p->pre_lat), dpl_lat(p->dpl_lat),
      trc_lat(p->trc_lat), num_banks(p->num_banks),
      num_cpus(p->num_cpus), last_dev(DR_NUM_DEVS+1),
      lastCmdIsRead(true), precharge(0), same_row_read_access(0), srr_after_read(0),
      srr_after_write(0), same_row_write_access(0), srw_after_read(0),
      srw_after_write(0), same_bank_read_access(0), sbr_after_read(0),
      sbr_after_write(0), same_bank_write_access(0), sbw_after_read(0),
      sbw_after_write(0), other_bank_read_access_hit(0), obr_after_read_hit(0),
      obr_after_write_hit(0), other_bank_write_access_hit(0),
      obw_after_read_hit(0), obw_after_write_hit(0), obr_after_read_miss(0),
      obr_after_write_miss(0),
      obw_after_read_miss(0), obw_after_write_miss(0), total_access(0),
      adjacent_access(0), adjacent_read(0), adjacent_write(0),
      command_overlapping(0), best_case(0), in_between_case(0), worst_case(0),
      full_overlapping(0), partial_overlapping(0), mem_access_details(false),
      memctrlpipe_enable(false), time_last_access(0)
{
    warn("This DRAM module has not been tested with the new memory system at all!");
        bank_size = (p->range.size() + 1) / num_banks;
        num_rows = bank_size / SD_ROW_SIZE; /* 0x1000 size of row 4Kbtye */
        active_row = new int[num_banks];
        last_bank = num_banks+1;
        last_row  = num_rows;
        busy_until = new Tick[num_banks];
        std::memset(busy_until,0,sizeof(Tick)*num_banks); /* initiliaze */

}

void
DRAMMemory::regStats()
{
    using namespace Stats;

    accesses
        .init(maxThreadsPerCPU)
        .name(name() + ".accesses")
        .desc("total number of accesses")
        .flags(total)
        ;

    bytesRequested
        .init(maxThreadsPerCPU)
        .name(name() + ".bytes_requested")
        .desc("total number of bytes requested")
        .flags(total)
        ;

    bytesSent
        .init(maxThreadsPerCPU)
        .name(name() + ".bytes_sent")
        .desc("total number of bytes sent")
        .flags(total)
        ;

    compressedAccesses
        .init(maxThreadsPerCPU)
        .name(name() + ".compressed_responses")
        .desc("total number of accesses that are compressed")
        .flags(total)
        ;

        // stats for power modelling
    cycles_nCKE
        .init(1)
        .name(name() + ".cycles_nCKE")
        .desc("cycles when CKE is low")
        .flags(total)
        ;

    cycles_all_precharge_CKE
        .init(1)
        .name(name() + ".cycles_all_precharge_CKE")
        .desc("cycles when all banks precharged")
        .flags(total)
        ;

    cycles_all_precharge_nCKE
        .init(1)
        .name(name() + ".cycles_all_precharge_nCKE")
        .desc("cycles when all banks precharged and CKE is low")
        .flags(total)
        ;

    cycles_bank_active_nCKE
        .init(1)
        .name(name() + ".cycles_bank_active_nCKE")
        .desc("cycles when banks active and CKE low")
        .flags(total)
        ;

        // we derive this from other stats later
        // so DR TODO for now this counter is unused
        cycles_avg_ACT
        .init(1)
        .name(name() + ".cycles_avg_ACT")
        .desc("avg cycles between ACT commands")
        .flags(total)
        ;

        cycles_read_out
        .init(1)
        .name(name() + ".cycles_read_out")
        .desc("cycles outputting read data")
        .flags(total)
        ;

        cycles_write_in
        .init(1)
        .name(name() + ".cycles_write_in")
        .desc("cycles inputting write data")
        .flags(total)
        ;

        cycles_between_misses
        .init(1)