iew.hh

M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作为模拟平台

    /** Unblocks Dispatch if the skid buffer is empty, and signals back to
     * other stages to unblock.
     */
    void unblock(unsigned thread_id);

    /** Determines proper actions to take given Dispatch's status. */
    void dispatch(unsigned tid);

    /** Dispatches instructions to IQ and LSQ. */
    void dispatchInsts(unsigned tid);

    /** Executes instructions. In the case of memory operations, it informs the
     * LSQ to execute the instructions. Also handles any redirects that occur
     * due to the executed instructions.
     */
    void executeInsts();

    /** Writebacks instructions. In our model, the instruction's execute()
     * function atomically reads registers, executes, and writes registers.
     * Thus this writeback only wakes up dependent instructions, and informs
     * the scoreboard of registers becoming ready.
     */
    void writebackInsts();

    /** Returns the number of valid, non-squashed instructions coming from
     * rename to dispatch.
     */
    unsigned validInstsFromRename();

    /** Reads the stall signals. */
    void readStallSignals(unsigned tid);

    /** Checks if any of the stall conditions are currently true. */
    bool checkStall(unsigned tid);

    /** Processes inputs and changes state accordingly. */
    void checkSignalsAndUpdate(unsigned tid);

    /** Removes instructions from rename from a thread's instruction list. */
    void emptyRenameInsts(unsigned tid);

    /** Sorts instructions coming from rename into lists separated by thread. */
    void sortInsts();

  public:
    /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
     * Writeback to run for one cycle.
     */
    void tick();

  private:
    /** Updates execution stats based on the instruction. */
    void updateExeInstStats(DynInstPtr &inst);

    /** Pointer to main time buffer used for backwards communication. */
    TimeBuffer<TimeStruct> *timeBuffer;

    /** Wire to write information heading to previous stages. */
    typename TimeBuffer<TimeStruct>::wire toFetch;

    /** Wire to get commit's output from backwards time buffer. */
    typename TimeBuffer<TimeStruct>::wire fromCommit;

    /** Wire to write information heading to previous stages. */
    typename TimeBuffer<TimeStruct>::wire toRename;

    /** Rename instruction queue interface. */
    TimeBuffer<RenameStruct> *renameQueue;

    /** Wire to get rename's output from rename queue. */
    typename TimeBuffer<RenameStruct>::wire fromRename;

    /** Issue stage queue. */
    TimeBuffer<IssueStruct> issueToExecQueue;

    /** Wire to read information from the issue stage time queue. */
    typename TimeBuffer<IssueStruct>::wire fromIssue;

    /**
     * IEW stage time buffer.  Holds ROB indices of instructions that
     * can be marked as completed.
     */
    TimeBuffer<IEWStruct> *iewQueue;

    /** Wire to write infromation heading to commit. */
    typename TimeBuffer<IEWStruct>::wire toCommit;

    /** Queue of all instructions coming from rename this cycle. */
    std::queue<DynInstPtr> insts[Impl::MaxThreads];

    /** Skid buffer between rename and IEW. */
    std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];

    /** Scoreboard pointer. */
    Scoreboard* scoreboard;

  private:
    /** CPU pointer. */
    O3CPU *cpu;

    /** Records if IEW has written to the time buffer this cycle, so that the
     * CPU can deschedule itself if there is no activity.
     */
    bool wroteToTimeBuffer;

    /** Source of possible stalls. */
    struct Stalls {
        bool commit;
    };

    /** Stages that are telling IEW to stall. */
    Stalls stalls[Impl::MaxThreads];

    /** Debug function to print instructions that are issued this cycle. */
    void printAvailableInsts();

  public:
    /** Instruction queue. */
    IQ instQueue;

    /** Load / store queue. */
    LSQ ldstQueue;

    /** Pointer to the functional unit pool. */
    FUPool *fuPool;
    /** Records if the LSQ needs to be updated on the next cycle, so that
     * IEW knows if there will be activity on the next cycle.
     */
    bool updateLSQNextCycle;

  private:
    /** Records if there is a fetch redirect on this cycle for each thread. */
    bool fetchRedirect[Impl::MaxThreads];

    /** Records if the queues have been changed (inserted or issued insts),
     * so that IEW knows to broadcast the updated amount of free entries.
     */
    bool updatedQueues;

    /** Commit to IEW delay, in ticks. */
    unsigned commitToIEWDelay;

    /** Rename to IEW delay, in ticks. */
    unsigned renameToIEWDelay;

    /**
     * Issue to execute delay, in ticks.  What this actually represents is
     * the amount of time it takes for an instruction to wake up, be
     * scheduled, and sent to a FU for execution.
     */
    unsigned issueToExecuteDelay;

    /** Width of dispatch, in instructions. */
    unsigned dispatchWidth;

    /** Width of issue, in instructions. */
    unsigned issueWidth;

    /** Index into queue of instructions being written back. */
    unsigned wbNumInst;

    /** Cycle number within the queue of instructions being written back.
     * Used in case there are too many instructions writing back at the current
     * cycle and writesbacks need to be scheduled for the future. See comments
     * in instToCommit().
     */
    unsigned wbCycle;

    /** Number of instructions in flight that will writeback. */

    /** Number of instructions in flight that will writeback. */
    int wbOutstanding;

    /** Writeback width. */
    unsigned wbWidth;

    /** Writeback width * writeback depth, where writeback depth is
     * the number of cycles of writing back instructions that can be
     * buffered. */
    unsigned wbMax;

    /** Number of active threads. */
    unsigned numThreads;

    /** Pointer to list of active threads. */
    std::list<unsigned> *activeThreads;

    /** Maximum size of the skid buffer. */
    unsigned skidBufferMax;

    /** Is this stage switched out. */
    bool switchedOut;

    /** Stat for total number of idle cycles. */
    Stats::Scalar<> iewIdleCycles;
    /** Stat for total number of squashing cycles. */
    Stats::Scalar<> iewSquashCycles;
    /** Stat for total number of blocking cycles. */
    Stats::Scalar<> iewBlockCycles;
    /** Stat for total number of unblocking cycles. */
    Stats::Scalar<> iewUnblockCycles;
    /** Stat for total number of instructions dispatched. */
    Stats::Scalar<> iewDispatchedInsts;
    /** Stat for total number of squashed instructions dispatch skips. */
    Stats::Scalar<> iewDispSquashedInsts;
    /** Stat for total number of dispatched load instructions. */
    Stats::Scalar<> iewDispLoadInsts;
    /** Stat for total number of dispatched store instructions. */
    Stats::Scalar<> iewDispStoreInsts;
    /** Stat for total number of dispatched non speculative instructions. */
    Stats::Scalar<> iewDispNonSpecInsts;
    /** Stat for number of times the IQ becomes full. */
    Stats::Scalar<> iewIQFullEvents;
    /** Stat for number of times the LSQ becomes full. */
    Stats::Scalar<> iewLSQFullEvents;
    /** Stat for total number of memory ordering violation events. */
    Stats::Scalar<> memOrderViolationEvents;
    /** Stat for total number of incorrect predicted taken branches. */
    Stats::Scalar<> predictedTakenIncorrect;
    /** Stat for total number of incorrect predicted not taken branches. */
    Stats::Scalar<> predictedNotTakenIncorrect;
    /** Stat for total number of mispredicted branches detected at execute. */
    Stats::Formula branchMispredicts;

    /** Stat for total number of executed instructions. */
    Stats::Scalar<> iewExecutedInsts;
    /** Stat for total number of executed load instructions. */
    Stats::Vector<> iewExecLoadInsts;
    /** Stat for total number of executed store instructions. */
//    Stats::Scalar<> iewExecStoreInsts;
    /** Stat for total number of squashed instructions skipped at execute. */
    Stats::Scalar<> iewExecSquashedInsts;
    /** Number of executed software prefetches. */
    Stats::Vector<> iewExecutedSwp;
    /** Number of executed nops. */
    Stats::Vector<> iewExecutedNop;
    /** Number of executed meomory references. */
    Stats::Vector<> iewExecutedRefs;
    /** Number of executed branches. */
    Stats::Vector<> iewExecutedBranches;
    /** Number of executed store instructions. */
    Stats::Formula iewExecStoreInsts;
    /** Number of instructions executed per cycle. */
    Stats::Formula iewExecRate;

    /** Number of instructions sent to commit. */
    Stats::Vector<> iewInstsToCommit;
    /** Number of instructions that writeback. */
    Stats::Vector<> writebackCount;
    /** Number of instructions that wake consumers. */
    Stats::Vector<> producerInst;
    /** Number of instructions that wake up from producers. */
    Stats::Vector<> consumerInst;
    /** Number of instructions that were delayed in writing back due
     * to resource contention.
     */
    Stats::Vector<> wbPenalized;
    /** Number of instructions per cycle written back. */
    Stats::Formula wbRate;
    /** Average number of woken instructions per writeback. */
    Stats::Formula wbFanout;
    /** Number of instructions per cycle delayed in writing back . */
    Stats::Formula wbPenalizedRate;
};

#endif // __CPU_O3_IEW_HH__