commit.hh

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#if FULL_SYSTEM    /** Handles processing an interrupt. */    void handleInterrupt();#endif // FULL_SYSTEM    /** Commits as many instructions as possible. */    void commitInsts();    /** Tries to commit the head ROB instruction passed in.     * @param head_inst The instruction to be committed.     */    bool commitHead(DynInstPtr &head_inst, unsigned inst_num);    /** Gets instructions from rename and inserts them into the ROB. */    void getInsts();    /** Insert all instructions from rename into skidBuffer */    void skidInsert();    /** Marks completed instructions using information sent from IEW. */    void markCompletedInsts();    /** Gets the thread to commit, based on the SMT policy. */    int getCommittingThread();    /** Returns the thread ID to use based on a round robin policy. */    int roundRobin();    /** Returns the thread ID to use based on an oldest instruction policy. */    int oldestReady();  public:    /** Returns the PC of the head instruction of the ROB.     * @todo: Probably remove this function as it returns only thread 0.     */    Addr readPC() { return PC[0]; }    /** Returns the PC of a specific thread. */    Addr readPC(unsigned tid) { return PC[tid]; }    /** Sets the PC of a specific thread. */    void setPC(Addr val, unsigned tid) { PC[tid] = val; }    /** Reads the micro PC of a specific thread. */    Addr readMicroPC(unsigned tid) { return microPC[tid]; }    /** Sets the micro PC of a specific thread */    void setMicroPC(Addr val, unsigned tid) { microPC[tid] = val; }    /** Reads the next PC of a specific thread. */    Addr readNextPC(unsigned tid) { return nextPC[tid]; }    /** Sets the next PC of a specific thread. */    void setNextPC(Addr val, unsigned tid) { nextPC[tid] = val; }    /** Reads the next NPC of a specific thread. */    Addr readNextNPC(unsigned tid) { return nextNPC[tid]; }    /** Sets the next NPC of a specific thread. */    void setNextNPC(Addr val, unsigned tid) { nextNPC[tid] = val; }    /** Reads the micro PC of a specific thread. */    Addr readNextMicroPC(unsigned tid) { return nextMicroPC[tid]; }    /** Sets the micro PC of a specific thread */    void setNextMicroPC(Addr val, unsigned tid) { nextMicroPC[tid] = val; }  private:    /** Time buffer interface. */    TimeBuffer<TimeStruct> *timeBuffer;    /** Wire to write information heading to previous stages. */    typename TimeBuffer<TimeStruct>::wire toIEW;    /** Wire to read information from IEW (for ROB). */    typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;    TimeBuffer<FetchStruct> *fetchQueue;    typename TimeBuffer<FetchStruct>::wire fromFetch;    /** IEW instruction queue interface. */    TimeBuffer<IEWStruct> *iewQueue;    /** Wire to read information from IEW queue. */    typename TimeBuffer<IEWStruct>::wire fromIEW;    /** Rename instruction queue interface, for ROB. */    TimeBuffer<RenameStruct> *renameQueue;    /** Wire to read information from rename queue. */    typename TimeBuffer<RenameStruct>::wire fromRename;  public:    /** ROB interface. */    ROB *rob;  private:    /** Pointer to O3CPU. */    O3CPU *cpu;    /** Vector of all of the threads. */    std::vector<Thread *> thread;    /** Records that commit has written to the time buffer this cycle. Used for     * the CPU to determine if it can deschedule itself if there is no activity.     */    bool wroteToTimeBuffer;    /** Records if the number of ROB entries has changed this cycle. If it has,     * then the number of free entries must be re-broadcast.     */    bool changedROBNumEntries[Impl::MaxThreads];    /** A counter of how many threads are currently squashing. */    int squashCounter;    /** Records if a thread has to squash this cycle due to a trap. */    bool trapSquash[Impl::MaxThreads];    /** Records if a thread has to squash this cycle due to an XC write. */    bool tcSquash[Impl::MaxThreads];    /** Priority List used for Commit Policy */    std::list<unsigned> priority_list;    /** IEW to Commit delay, in ticks. */    unsigned iewToCommitDelay;    /** Commit to IEW delay, in ticks. */    unsigned commitToIEWDelay;    /** Rename to ROB delay, in ticks. */    unsigned renameToROBDelay;    unsigned fetchToCommitDelay;    /** Rename width, in instructions.  Used so ROB knows how many     *  instructions to get from the rename instruction queue.     */    unsigned renameWidth;    /** Commit width, in instructions. */    unsigned commitWidth;    /** Number of Reorder Buffers */    unsigned numRobs;    /** Number of Active Threads */    unsigned numThreads;    /** Is a drain pending. */    bool drainPending;    /** Is commit switched out. */    bool switchedOut;    /** The latency to handle a trap.  Used when scheduling trap     * squash event.     */    Tick trapLatency;    /** The interrupt fault. */    Fault interrupt;    /** The commit PC of each thread.  Refers to the instruction that     * is currently being processed/committed.     */    Addr PC[Impl::MaxThreads];    /** The commit micro PC of each thread.  Refers to the instruction that     * is currently being processed/committed.     */    Addr microPC[Impl::MaxThreads];    /** The next PC of each thread. */    Addr nextPC[Impl::MaxThreads];    /** The next NPC of each thread. */    Addr nextNPC[Impl::MaxThreads];    /** The next micro PC of each thread. */    Addr nextMicroPC[Impl::MaxThreads];    /** The sequence number of the youngest valid instruction in the ROB. */    InstSeqNum youngestSeqNum[Impl::MaxThreads];    /** Records if there is a trap currently in flight. */    bool trapInFlight[Impl::MaxThreads];    /** Records if there were any stores committed this cycle. */    bool committedStores[Impl::MaxThreads];    /** Records if commit should check if the ROB is truly empty (see        commit_impl.hh). */    bool checkEmptyROB[Impl::MaxThreads];    /** Pointer to the list of active threads. */    std::list<unsigned> *activeThreads;    /** Rename map interface. */    RenameMap *renameMap[Impl::MaxThreads];    /** Updates commit stats based on this instruction. */    void updateComInstStats(DynInstPtr &inst);    /** Stat for the total number of committed instructions. */    Stats::Scalar<> commitCommittedInsts;    /** Stat for the total number of squashed instructions discarded by commit.     */    Stats::Scalar<> commitSquashedInsts;    /** Stat for the total number of times commit is told to squash.     * @todo: Actually increment this stat.     */    Stats::Scalar<> commitSquashEvents;    /** Stat for the total number of times commit has had to stall due to a non-     * speculative instruction reaching the head of the ROB.     */    Stats::Scalar<> commitNonSpecStalls;    /** Stat for the total number of branch mispredicts that caused a squash. */    Stats::Scalar<> branchMispredicts;    /** Distribution of the number of committed instructions each cycle. */    Stats::Distribution<> numCommittedDist;    /** Total number of instructions committed. */    Stats::Vector<> statComInst;    /** Total number of software prefetches committed. */    Stats::Vector<> statComSwp;    /** Stat for the total number of committed memory references. */    Stats::Vector<> statComRefs;    /** Stat for the total number of committed loads. */    Stats::Vector<> statComLoads;    /** Total number of committed memory barriers. */    Stats::Vector<> statComMembars;    /** Total number of committed branches. */    Stats::Vector<> statComBranches;    /** Number of cycles where the commit bandwidth limit is reached. */    Stats::Scalar<> commitEligibleSamples;    /** Number of instructions not committed due to bandwidth limits. */    Stats::Vector<> commitEligible;};#endif // __CPU_O3_COMMIT_HH__

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