impl.hh

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· HH 代码 · 共 93 行

/*
 * Copyright (c) 2004, 2005
 * The Regents of The University of Michigan
 * All Rights Reserved
 *
 * This code is part of the M5 simulator.
 *
 * Permission is granted to use, copy, create derivative works and
 * redistribute this software and such derivative works for any
 * purpose, so long as the copyright notice above, this grant of
 * permission, and the disclaimer below appear in all copies made; and
 * so long as the name of The University of Michigan is not used in
 * any advertising or publicity pertaining to the use or distribution
 * of this software without specific, written prior authorization.
 *
 * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
 * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
 * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
 * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
 * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
 * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
 * DAMAGES.
 *
 * Authors: Gabe M. Black
 */

#ifndef __CPU_O3_SPARC_IMPL_HH__
#define __CPU_O3_SPARC_IMPL_HH__

#include "arch/sparc/isa_traits.hh"

#include "cpu/o3/sparc/params.hh"
#include "cpu/o3/cpu_policy.hh"


// Forward declarations.
template <class Impl>
class SparcDynInst;

template <class Impl>
class SparcO3CPU;

/** Implementation specific struct that defines several key types to the
 *  CPU, the stages within the CPU, the time buffers, and the DynInst.
 *  The struct defines the ISA, the CPU policy, the specific DynInst, the
 *  specific O3CPU, and all of the structs from the time buffers to do
 *  communication.
 *  This is one of the key things that must be defined for each hardware
 *  specific CPU implementation.
 */
struct SparcSimpleImpl
{
    /** The type of MachInst. */
    typedef TheISA::MachInst MachInst;

    /** The CPU policy to be used, which defines all of the CPU stages. */
    typedef SimpleCPUPolicy<SparcSimpleImpl> CPUPol;

    /** The DynInst type to be used. */
    typedef SparcDynInst<SparcSimpleImpl> DynInst;

    /** The refcounted DynInst pointer to be used.  In most cases this is
     *  what should be used, and not DynInst *.
     */
    typedef RefCountingPtr<DynInst> DynInstPtr;

    /** The O3CPU type to be used. */
    typedef SparcO3CPU<SparcSimpleImpl> O3CPU;

    /** Same typedef, but for CPUType.  BaseDynInst may not always use
     * an O3 CPU, so it's clearer to call it CPUType instead in that
     * case.
     */
    typedef O3CPU CPUType;

    /** The Params to be passed to each stage. */
    typedef SparcSimpleParams Params;

    enum {
      MaxWidth = 8,
      MaxThreads = 4
    };
};

/** The O3Impl to be used. */
typedef SparcSimpleImpl O3CPUImpl;

#endif // __CPU_O3_SPARC_IMPL_HH__