sconscript

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 代码 · 共 105 行

# -*- mode:python -*-

# Copyright (c) 2006
# The Regents of The University of Michigan
# All Rights Reserved
#
# This code is part of the M5 simulator.
#
# Permission is granted to use, copy, create derivative works and
# redistribute this software and such derivative works for any
# purpose, so long as the copyright notice above, this grant of
# permission, and the disclaimer below appear in all copies made; and
# so long as the name of The University of Michigan is not used in any
# advertising or publicity pertaining to the use or distribution of
# this software without specific, written prior authorization.
#
# THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
# UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
# WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
# EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
# LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
# INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
# ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
# IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
# DAMAGES.
#
# Authors: Nathan L. Binkert

import sys

Import('*')

if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
    Source('2bit_local_pred.cc')
    Source('btb.cc')
    Source('ras.cc')
    Source('tournament_pred.cc')

    TraceFlag('CommitRate')
    TraceFlag('IEW')
    TraceFlag('IQ')

if 'O3CPU' in env['CPU_MODELS']:
    SimObject('FUPool.py')
    SimObject('FuncUnitConfig.py')
    SimObject('O3CPU.py')

    Source('base_dyn_inst.cc')
    Source('bpred_unit.cc')
    Source('commit.cc')
    Source('cpu.cc')
    Source('decode.cc')
    Source('fetch.cc')
    Source('free_list.cc')
    Source('fu_pool.cc')
    Source('iew.cc')
    Source('inst_queue.cc')
    Source('lsq.cc')
    Source('lsq_unit.cc')
    Source('mem_dep_unit.cc')
    Source('rename.cc')
    Source('rename_map.cc')
    Source('rob.cc')
    Source('scoreboard.cc')
    Source('store_set.cc')

    TraceFlag('FreeList')
    TraceFlag('LSQ')
    TraceFlag('LSQUnit')
    TraceFlag('MemDepUnit')
    TraceFlag('O3CPU')
    TraceFlag('ROB')
    TraceFlag('Rename')
    TraceFlag('Scoreboard')
    TraceFlag('StoreSet')
    TraceFlag('Writeback')

    CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit',
        'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
        'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ])

    if env['TARGET_ISA'] == 'alpha':
        Source('alpha/cpu.cc')
        Source('alpha/cpu_builder.cc')
        Source('alpha/dyn_inst.cc')
        Source('alpha/thread_context.cc')
    elif env['TARGET_ISA'] == 'mips':
        Source('mips/cpu.cc')
        Source('mips/cpu_builder.cc')
        Source('mips/dyn_inst.cc')
        Source('mips/thread_context.cc')
    elif env['TARGET_ISA'] == 'sparc':
        Source('sparc/cpu.cc')
        Source('sparc/cpu_builder.cc')
        Source('sparc/dyn_inst.cc')
        Source('sparc/thread_context.cc')
    else:
        sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])

    if env['USE_CHECKER']:
        SimObject('O3Checker.py')
        Source('checker_builder.cc')