base_dyn_inst.hh

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· HH 代码 · 共 1,003 行 · 第 1/3 页

    void clearIssued() { status.reset(Issued); }

    /** Sets this instruction as executed. */
    void setExecuted() { status.set(Executed); }

    /** Returns whether or not this instruction has executed. */
    bool isExecuted() const { return status[Executed]; }

    /** Sets this instruction as ready to commit. */
    void setCanCommit() { status.set(CanCommit); }

    /** Clears this instruction as being ready to commit. */
    void clearCanCommit() { status.reset(CanCommit); }

    /** Returns whether or not this instruction is ready to commit. */
    bool readyToCommit() const { return status[CanCommit]; }

    void setAtCommit() { status.set(AtCommit); }

    bool isAtCommit() { return status[AtCommit]; }

    /** Sets this instruction as committed. */
    void setCommitted() { status.set(Committed); }

    /** Returns whether or not this instruction is committed. */
    bool isCommitted() const { return status[Committed]; }

    /** Sets this instruction as squashed. */
    void setSquashed() { status.set(Squashed); }

    /** Returns whether or not this instruction is squashed. */
    bool isSquashed() const { return status[Squashed]; }

    //Instruction Queue Entry
    //-----------------------
    /** Sets this instruction as a entry the IQ. */
    void setInIQ() { status.set(IqEntry); }

    /** Sets this instruction as a entry the IQ. */
    void clearInIQ() { status.reset(IqEntry); }

    /** Returns whether or not this instruction has issued. */
    bool isInIQ() const { return status[IqEntry]; }

    /** Sets this instruction as squashed in the IQ. */
    void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}

    /** Returns whether or not this instruction is squashed in the IQ. */
    bool isSquashedInIQ() const { return status[SquashedInIQ]; }


    //Load / Store Queue Functions
    //-----------------------
    /** Sets this instruction as a entry the LSQ. */
    void setInLSQ() { status.set(LsqEntry); }

    /** Sets this instruction as a entry the LSQ. */
    void removeInLSQ() { status.reset(LsqEntry); }

    /** Returns whether or not this instruction is in the LSQ. */
    bool isInLSQ() const { return status[LsqEntry]; }

    /** Sets this instruction as squashed in the LSQ. */
    void setSquashedInLSQ() { status.set(SquashedInLSQ);}

    /** Returns whether or not this instruction is squashed in the LSQ. */
    bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }


    //Reorder Buffer Functions
    //-----------------------
    /** Sets this instruction as a entry the ROB. */
    void setInROB() { status.set(RobEntry); }

    /** Sets this instruction as a entry the ROB. */
    void clearInROB() { status.reset(RobEntry); }

    /** Returns whether or not this instruction is in the ROB. */
    bool isInROB() const { return status[RobEntry]; }

    /** Sets this instruction as squashed in the ROB. */
    void setSquashedInROB() { status.set(SquashedInROB); }

    /** Returns whether or not this instruction is squashed in the ROB. */
    bool isSquashedInROB() const { return status[SquashedInROB]; }

    /** Read the PC of this instruction. */
    const Addr readPC() const { return PC; }

    /**Read the micro PC of this instruction. */
    const Addr readMicroPC() const { return microPC; }

    /** Set the next PC of this instruction (its actual target). */
    void setNextPC(Addr val)
    {
        nextPC = val;
    }

    /** Set the next NPC of this instruction (the target in Mips or Sparc).*/
    void setNextNPC(Addr val)
    {
#if ISA_HAS_DELAY_SLOT
        nextNPC = val;
#endif
    }

    void setNextMicroPC(Addr val)
    {
        nextMicroPC = val;
    }

    /** Sets the ASID. */
    void setASID(short addr_space_id) { asid = addr_space_id; }

    /** Sets the thread id. */
    void setTid(unsigned tid) { threadNumber = tid; }

    /** Sets the pointer to the thread state. */
    void setThreadState(ImplState *state) { thread = state; }

    /** Returns the thread context. */
    ThreadContext *tcBase() { return thread->getTC(); }

  private:
    /** Instruction effective address.
     *  @todo: Consider if this is necessary or not.
     */
    Addr instEffAddr;

    /** Whether or not the effective address calculation is completed.
     *  @todo: Consider if this is necessary or not.
     */
    bool eaCalcDone;

    /** Is this instruction's memory access uncacheable. */
    bool isUncacheable;

    /** Has this instruction generated a memory request. */
    bool reqMade;

  public:
    /** Sets the effective address. */
    void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }

    /** Returns the effective address. */
    const Addr &getEA() const { return instEffAddr; }

    /** Returns whether or not the eff. addr. calculation has been completed. */
    bool doneEACalc() { return eaCalcDone; }

    /** Returns whether or not the eff. addr. source registers are ready. */
    bool eaSrcsReady();

    /** Whether or not the memory operation is done. */
    bool memOpDone;

    /** Is this instruction's memory access uncacheable. */
    bool uncacheable() { return isUncacheable; }

    /** Has this instruction generated a memory request. */
    bool hasRequest() { return reqMade; }

  public:
    /** Load queue index. */
    int16_t lqIdx;

    /** Store queue index. */
    int16_t sqIdx;

    /** Iterator pointing to this BaseDynInst in the list of all insts. */
    ListIt instListIt;

    /** Returns iterator to this instruction in the list of all insts. */
    ListIt &getInstListIt() { return instListIt; }

    /** Sets iterator for this instruction in the list of all insts. */
    void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }

  public:
    /** Returns the number of consecutive store conditional failures. */
    unsigned readStCondFailures()
    { return thread->storeCondFailures; }

    /** Sets the number of consecutive store conditional failures. */
    void setStCondFailures(unsigned sc_failures)
    { thread->storeCondFailures = sc_failures; }
};

template<class Impl>
Fault
BaseDynInst<Impl>::translateDataReadAddr(Addr vaddr, Addr &paddr,
        int size, unsigned flags)
{
    if (traceData) {
        traceData->setAddr(vaddr);
    }

    reqMade = true;
    Request *req = new Request();
    req->setVirt(asid, vaddr, size, flags, PC);
    req->setThreadContext(thread->readCpuId(), threadNumber);

    fault = cpu->translateDataReadReq(req, thread);

    if (fault == NoFault)
        paddr = req->getPaddr();

    delete req;
    return fault;
}

template<class Impl>
template<class T>
inline Fault
BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
{
    reqMade = true;
    Request *req = new Request();
    req->setVirt(asid, addr, sizeof(T), flags, this->PC);
    req->setThreadContext(thread->readCpuId(), threadNumber);

    fault = cpu->translateDataReadReq(req, thread);

    if (req->isUncacheable())
        isUncacheable = true;

    if (fault == NoFault) {
        effAddr = req->getVaddr();
        effAddrValid = true;
        physEffAddr = req->getPaddr();
        memReqFlags = req->getFlags();

#if 0
        if (cpu->system->memctrl->badaddr(physEffAddr)) {
            fault = TheISA::genMachineCheckFault();
            data = (T)-1;
            this->setExecuted();
        } else {
            fault = cpu->read(req, data, lqIdx);
        }
#else
        fault = cpu->read(req, data, lqIdx);
#endif
    } else {
        // Return a fixed value to keep simulation deterministic even
        // along misspeculated paths.
        data = (T)-1;

        // Commit will have to clean up whatever happened.  Set this
        // instruction as executed.
        this->setExecuted();
        delete req;
    }

    if (traceData) {
        traceData->setAddr(addr);
        traceData->setData(data);
    }

    return fault;
}

template<class Impl>
Fault
BaseDynInst<Impl>::translateDataWriteAddr(Addr vaddr, Addr &paddr,
        int size, unsigned flags)
{
    if (traceData) {
        traceData->setAddr(vaddr);
    }

    reqMade = true;
    Request *req = new Request();
    req->setVirt(asid, vaddr, size, flags, PC);
    req->setThreadContext(thread->readCpuId(), threadNumber);

    fault = cpu->translateDataWriteReq(req, thread);

    if (fault == NoFault)
        paddr = req->getPaddr();

    delete req;
    return fault;
}

template<class Impl>
template<class T>
inline Fault
BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
    if (traceData) {
        traceData->setAddr(addr);
        traceData->setData(data);
    }

    reqMade = true;
    Request *req = new Request();
    req->setVirt(asid, addr, sizeof(T), flags, this->PC);
    req->setThreadContext(thread->readCpuId(), threadNumber);

    fault = cpu->translateDataWriteReq(req, thread);

    if (req->isUncacheable())
        isUncacheable = true;

    if (fault == NoFault) {
        effAddr = req->getVaddr();
        effAddrValid = true;
        physEffAddr = req->getPaddr();
        memReqFlags = req->getFlags();

        if (req->isCondSwap()) {
            assert(res);
            req->setExtraData(*res);
        }
#if 0
        if (cpu->system->memctrl->badaddr(physEffAddr)) {
            fault = TheISA::genMachineCheckFault();
        } else {
            fault = cpu->write(req, data, sqIdx);
        }
#else
        fault = cpu->write(req, data, sqIdx);
#endif
    } else {
        delete req;
    }

    return fault;
}

#endif // __CPU_BASE_DYN_INST_HH__