tsunami_cchip.cc

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· CC 代码 · 共 529 行 · 第 1/2 页

              itintr = (pkt->get<uint64_t>() >> 4) & 0xF;
            if (itintr) {
                  clearITI(itintr);
                supportedWrite = true;
            }

              // ignore NXMs
              if (pkt->get<uint64_t>() & 0x10000000)
                  supportedWrite = true;

            if(!supportedWrite)
                  panic("TSDEV_CC_MISC write not implemented\n");

            break;
            case TSDEV_CC_AAR0:
            case TSDEV_CC_AAR1:
            case TSDEV_CC_AAR2:
            case TSDEV_CC_AAR3:
                panic("TSDEV_CC_AARx write not implemeted\n");
            case TSDEV_CC_DIM0:
            case TSDEV_CC_DIM1:
            case TSDEV_CC_DIM2:
            case TSDEV_CC_DIM3:
                int number;
                if(regnum == TSDEV_CC_DIM0)
                    number = 0;
                else if(regnum == TSDEV_CC_DIM1)
                    number = 1;
                else if(regnum == TSDEV_CC_DIM2)
                    number = 2;
                else
                    number = 3;

                uint64_t bitvector;
                uint64_t olddim;
                uint64_t olddir;

                olddim = dim[number];
                olddir = dir[number];
                dim[number] = pkt->get<uint64_t>();
                dir[number] = dim[number] & drir;
                for(int x = 0; x < 64; x++)
                {
                    bitvector = ULL(1) << x;
                    // Figure out which bits have changed
                    if ((dim[number] & bitvector) != (olddim & bitvector))
                    {
                        // The bit is now set and it wasn't before (set)
                        if((dim[number] & bitvector) && (dir[number] & bitvector))
                        {
                          tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
                          DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n");
                        }
                        else if ((olddir & bitvector) &&
                                !(dir[number] & bitvector))
                        {
                            // The bit was set and now its now clear and
                            // we were interrupting on that bit before
                            tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
                          DPRINTF(Tsunami, "dim write resulting in clear"
                                    " dir interrupt to cpu %d\n",
                                    x);

                        }


                    }
                }
                break;
            case TSDEV_CC_DIR0:
            case TSDEV_CC_DIR1:
            case TSDEV_CC_DIR2:
            case TSDEV_CC_DIR3:
                panic("TSDEV_CC_DIR write not implemented\n");
            case TSDEV_CC_DRIR:
                panic("TSDEV_CC_DRIR write not implemented\n");
            case TSDEV_CC_PRBEN:
                panic("TSDEV_CC_PRBEN write not implemented\n");
            case TSDEV_CC_IIC0:
            case TSDEV_CC_IIC1:
            case TSDEV_CC_IIC2:
            case TSDEV_CC_IIC3:
                panic("TSDEV_CC_IICx write not implemented\n");
            case TSDEV_CC_MPR0:
            case TSDEV_CC_MPR1:
            case TSDEV_CC_MPR2:
            case TSDEV_CC_MPR3:
                panic("TSDEV_CC_MPRx write not implemented\n");
            case TSDEV_CC_IPIR:
                clearIPI(pkt->get<uint64_t>());
                break;
            case TSDEV_CC_ITIR:
                clearITI(pkt->get<uint64_t>());
                break;
            case TSDEV_CC_IPIQ:
                reqIPI(pkt->get<uint64_t>());
                break;
            default:
              panic("default in cchip read reached, accessing 0x%x\n");
        }  // swtich(regnum)
    } // not BIG_TSUNAMI write
    pkt->makeAtomicResponse();
    return pioDelay;
}

void
TsunamiCChip::clearIPI(uint64_t ipintr)
{
    int numcpus = sys->threadContexts.size();
    assert(numcpus <= Tsunami::Max_CPUs);

    if (ipintr) {
        for (int cpunum=0; cpunum < numcpus; cpunum++) {
            // Check each cpu bit
            uint64_t cpumask = ULL(1) << cpunum;
            if (ipintr & cpumask) {
                // Check if there is a pending ipi
                if (ipint & cpumask) {
                    ipint &= ~cpumask;
                    tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
                    DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
                }
                else
                    warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
            }
        }
    }
    else
        panic("Big IPI Clear, but not processors indicated\n");
}

void
TsunamiCChip::clearITI(uint64_t itintr)
{
    int numcpus = sys->threadContexts.size();
    assert(numcpus <= Tsunami::Max_CPUs);

    if (itintr) {
        for (int i=0; i < numcpus; i++) {
            uint64_t cpumask = ULL(1) << i;
            if (itintr & cpumask & itint) {
                tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
                itint &= ~cpumask;
                DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
            }
        }
    }
    else
        panic("Big ITI Clear, but not processors indicated\n");
}

void
TsunamiCChip::reqIPI(uint64_t ipreq)
{
    int numcpus = sys->threadContexts.size();
    assert(numcpus <= Tsunami::Max_CPUs);

    if (ipreq) {
        for (int cpunum=0; cpunum < numcpus; cpunum++) {
            // Check each cpu bit
            uint64_t cpumask = ULL(1) << cpunum;
            if (ipreq & cpumask) {
                // Check if there is already an ipi (bits 8:11)
                if (!(ipint & cpumask)) {
                    ipint  |= cpumask;
                    tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
                    DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
                }
                else
                    warn("post IPI for CPU=%d, but IPI already\n", cpunum);
            }
        }
    }
    else
        panic("Big IPI Request, but not processors indicated\n");
}


void
TsunamiCChip::postRTC()
{
    int size = sys->threadContexts.size();
    assert(size <= Tsunami::Max_CPUs);

    for (int i = 0; i < size; i++) {
        uint64_t cpumask = ULL(1) << i;
       if (!(cpumask & itint)) {
           itint |= cpumask;
           tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
           DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d\n", i);
       }
    }

}

void
TsunamiCChip::postDRIR(uint32_t interrupt)
{
    uint64_t bitvector = ULL(1) << interrupt;
    uint64_t size = sys->threadContexts.size();
    assert(size <= Tsunami::Max_CPUs);
    drir |= bitvector;

    for(int i=0; i < size; i++) {
        dir[i] = dim[i] & drir;
       if (dim[i] & bitvector) {
              tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
              DPRINTF(Tsunami, "posting dir interrupt to cpu %d,"
                        "interrupt %d\n",i, interrupt);
       }
    }
}

void
TsunamiCChip::clearDRIR(uint32_t interrupt)
{
    uint64_t bitvector = ULL(1) << interrupt;
    uint64_t size = sys->threadContexts.size();
    assert(size <= Tsunami::Max_CPUs);

    if (drir & bitvector)
    {
        drir &= ~bitvector;
        for(int i=0; i < size; i++) {
           if (dir[i] & bitvector) {
               tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt);
               DPRINTF(Tsunami, "clearing dir interrupt to cpu %d,"
                    "interrupt %d\n",i, interrupt);

           }
           dir[i] = dim[i] & drir;
        }
    }
    else
        DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
}


void
TsunamiCChip::serialize(std::ostream &os)
{
    SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
    SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
    SERIALIZE_SCALAR(ipint);
    SERIALIZE_SCALAR(itint);
    SERIALIZE_SCALAR(drir);
}

void
TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
{
    UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
    UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
    UNSERIALIZE_SCALAR(ipint);
    UNSERIALIZE_SCALAR(itint);
    UNSERIALIZE_SCALAR(drir);
}

TsunamiCChip *
TsunamiCChipParams::create()
{
    return new TsunamiCChip(this);
}