i8254xgbe_defs.hh

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/*
 * Copyright (c) 2006
 * The Regents of The University of Michigan
 * All Rights Reserved
 *
 * This code is part of the M5 simulator.
 *
 * Permission is granted to use, copy, create derivative works and
 * redistribute this software and such derivative works for any
 * purpose, so long as the copyright notice above, this grant of
 * permission, and the disclaimer below appear in all copies made; and
 * so long as the name of The University of Michigan is not used in
 * any advertising or publicity pertaining to the use or distribution
 * of this software without specific, written prior authorization.
 *
 * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
 * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
 * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
 * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
 * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
 * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
 * DAMAGES.
 *
 * Authors: Ali G. Saidi
 */

/* @file
 * Register and structure descriptions for Intel's 8254x line of gigabit ethernet controllers.
 */
#include "base/bitfield.hh"

namespace iGbReg {


// Registers used by the Intel GbE NIC
const uint32_t REG_CTRL     = 0x00000;
const uint32_t REG_STATUS   = 0x00008;
const uint32_t REG_EECD     = 0x00010;
const uint32_t REG_EERD     = 0x00014;
const uint32_t REG_CTRL_EXT = 0x00018;
const uint32_t REG_MDIC     = 0x00020;
const uint32_t REG_FCAL     = 0x00028;
const uint32_t REG_FCAH     = 0x0002C;
const uint32_t REG_FCT      = 0x00030;
const uint32_t REG_VET      = 0x00038;
const uint32_t REG_PBA      = 0x01000;
const uint32_t REG_ICR      = 0x000C0;
const uint32_t REG_ITR      = 0x000C4;
const uint32_t REG_ICS      = 0x000C8;
const uint32_t REG_IMS      = 0x000D0;
const uint32_t REG_IMC      = 0x000D8;
const uint32_t REG_IAM      = 0x000E0;
const uint32_t REG_RCTL     = 0x00100;
const uint32_t REG_FCTTV    = 0x00170;
const uint32_t REG_TIPG     = 0x00410;
const uint32_t REG_AIFS     = 0x00458;
const uint32_t REG_LEDCTL   = 0x00e00;
const uint32_t REG_FCRTL    = 0x02160;
const uint32_t REG_FCRTH    = 0x02168;
const uint32_t REG_RDBAL    = 0x02800;
const uint32_t REG_RDBAH    = 0x02804;
const uint32_t REG_RDLEN    = 0x02808;
const uint32_t REG_RDH      = 0x02810;
const uint32_t REG_RDT      = 0x02818;
const uint32_t REG_RDTR     = 0x02820;
const uint32_t REG_RXDCTL   = 0x02828;
const uint32_t REG_RADV     = 0x0282C;
const uint32_t REG_TCTL     = 0x00400;
const uint32_t REG_TDBAL    = 0x03800;
const uint32_t REG_TDBAH    = 0x03804;
const uint32_t REG_TDLEN    = 0x03808;
const uint32_t REG_TDH      = 0x03810;
const uint32_t REG_TDT      = 0x03818;
const uint32_t REG_TIDV     = 0x03820;
const uint32_t REG_TXDCTL   = 0x03828;
const uint32_t REG_TADV     = 0x0382C;
const uint32_t REG_CRCERRS  = 0x04000;
const uint32_t REG_RXCSUM   = 0x05000;
const uint32_t REG_MTA      = 0x05200;
const uint32_t REG_RAL      = 0x05400;
const uint32_t REG_RAH      = 0x05404;
const uint32_t REG_VFTA     = 0x05600;

const uint32_t REG_WUC      = 0x05800;
const uint32_t REG_MANC     = 0x05820;

const uint8_t EEPROM_READ_OPCODE_SPI    = 0x03;
const uint8_t EEPROM_RDSR_OPCODE_SPI    = 0x05;
const uint8_t EEPROM_SIZE               = 64;
const uint16_t EEPROM_CSUM              = 0xBABA;

const uint8_t VLAN_FILTER_TABLE_SIZE    = 128;
const uint8_t RCV_ADDRESS_TABLE_SIZE    = 16;
const uint8_t MULTICAST_TABLE_SIZE      = 128;
const uint32_t STATS_REGS_SIZE           = 0x124;


// Registers in that are accessed in the PHY
const uint8_t PHY_PSTATUS       = 0x1;
const uint8_t PHY_PID           = 0x2;
const uint8_t PHY_EPID          = 0x3;
const uint8_t PHY_GSTATUS       = 10;
const uint8_t PHY_EPSTATUS      = 15;
const uint8_t PHY_AGC           = 18;

// Receive Descriptor Status Flags
const uint8_t RXDS_PIF         = 0x80;
const uint8_t RXDS_IPCS        = 0x40;
const uint8_t RXDS_TCPCS       = 0x20;
const uint8_t RXDS_UDPCS       = 0x10;
const uint8_t RXDS_VP          = 0x08;
const uint8_t RXDS_IXSM        = 0x04;
const uint8_t RXDS_EOP         = 0x02;
const uint8_t RXDS_DD          = 0x01;

// Receive Descriptor Error Flags
const uint8_t RXDE_RXE         = 0x80;
const uint8_t RXDE_IPE         = 0x40;
const uint8_t RXDE_TCPE        = 0x20;
const uint8_t RXDE_SEQ         = 0x04;
const uint8_t RXDE_SE          = 0x02;
const uint8_t RXDE_CE          = 0x01;

// Interrupt types
enum IntTypes
{
    IT_NONE    = 0x00000, //dummy value
    IT_TXDW    = 0x00001,
    IT_TXQE    = 0x00002,
    IT_LSC     = 0x00004,
    IT_RXSEQ   = 0x00008,
    IT_RXDMT   = 0x00010,
    IT_RXO     = 0x00040,
    IT_RXT     = 0x00080,
    IT_MADC    = 0x00200,
    IT_RXCFG   = 0x00400,
    IT_GPI0    = 0x02000,
    IT_GPI1    = 0x04000,
    IT_TXDLOW  = 0x08000,
    IT_SRPD    = 0x10000,
    IT_ACK     = 0x20000
};

// Receive Descriptor struct
struct RxDesc {
    Addr buf;
    uint16_t len;
    uint16_t csum;
    uint8_t status;
    uint8_t errors;
    uint16_t vlan;
};

struct TxDesc {
    uint64_t d1;
    uint64_t d2;
};

namespace TxdOp {
const uint8_t TXD_CNXT = 0x0;
const uint8_t TXD_DATA = 0x1;

bool isLegacy(TxDesc *d) { return !bits(d->d2,29,29); }
uint8_t getType(TxDesc *d) { return bits(d->d2, 23,20); }
bool isContext(TxDesc *d) { return !isLegacy(d) && getType(d) == TXD_CNXT; }
bool isData(TxDesc *d) { return !isLegacy(d) && getType(d) == TXD_DATA; }

Addr getBuf(TxDesc *d) { assert(isLegacy(d) || isData(d)); return d->d1; }
Addr getLen(TxDesc *d) { if (isLegacy(d)) return bits(d->d2,15,0); else return bits(d->d2, 19,0); }
void setDd(TxDesc *d)
{
    replaceBits(d->d2, 35, 32, ULL(1));
}

bool ide(TxDesc *d)  { return bits(d->d2, 31,31); }
bool vle(TxDesc *d)  { assert(isLegacy(d) || isData(d)); return bits(d->d2, 30,30); }
bool rs(TxDesc *d)   { return bits(d->d2, 27,27); }
bool ic(TxDesc *d)   { assert(isLegacy(d) || isData(d)); return isLegacy(d) && bits(d->d2, 26,26); }
bool tse(TxDesc *d)  { return (isData(d) || isContext(d)) && bits(d->d2, 26,26); }
bool ifcs(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 25,25); }
bool eop(TxDesc *d)  { assert(isLegacy(d) || isData(d)); return bits(d->d2, 24,24); }
bool ip(TxDesc *d)   { assert(isContext(d)); return bits(d->d2, 25,25); }
bool tcp(TxDesc *d)  { assert(isContext(d)); return bits(d->d2, 24,24); }

uint8_t getCso(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 23,16); }
uint8_t getCss(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 47,40); }

bool ixsm(TxDesc *d)  { return isData(d) && bits(d->d2, 40,40); }
bool txsm(TxDesc *d)  { return isData(d) && bits(d->d2, 41,41); }

int tucse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,63,48); }
int tucso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,47,40); }
int tucss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,39,32); }
int ipcse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,31,16); }
int ipcso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,15,8); }
int ipcss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,7,0); }
int mss(TxDesc *d) { assert(isContext(d)); return bits(d->d2,63,48); }
int hdrlen(TxDesc *d) { assert(isContext(d)); return bits(d->d2,47,40); }
} // namespace TxdOp


#define ADD_FIELD32(NAME, OFFSET, BITS) \
    inline uint32_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
    inline void NAME(uint32_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }

#define ADD_FIELD64(NAME, OFFSET, BITS) \
    inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
    inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }

struct Regs {
    template<class T>
    struct Reg {
        T _data;
        T operator()() { return _data; }
        const Reg<T> &operator=(T d) { _data = d; return *this;}
        bool operator==(T d) { return d == _data; }
        void operator()(T d) { _data = d; }
        Reg() { _data = 0; }
        void serialize(std::ostream &os)
        {
            SERIALIZE_SCALAR(_data);
        }
        void unserialize(Checkpoint *cp, const std::string &section)
        {
            UNSERIALIZE_SCALAR(_data);
        }
    };

    struct CTRL : public Reg<uint32_t> { // 0x0000 CTRL Register
        using Reg<uint32_t>::operator=;
        ADD_FIELD32(fd,0,1);       // full duplex
        ADD_FIELD32(bem,1,1);      // big endian mode
        ADD_FIELD32(pcipr,2,1);    // PCI priority
        ADD_FIELD32(lrst,3,1);     // link reset
        ADD_FIELD32(tme,4,1);      // test mode enable
        ADD_FIELD32(asde,5,1);     // Auto-speed detection
        ADD_FIELD32(slu,6,1);      // Set link up
        ADD_FIELD32(ilos,7,1);     // invert los-of-signal
        ADD_FIELD32(speed,8,2);    // speed selection bits
        ADD_FIELD32(be32,10,1);    // big endian mode 32
        ADD_FIELD32(frcspd,11,1);  // force speed
        ADD_FIELD32(frcdpx,12,1);  // force duplex
        ADD_FIELD32(duden,13,1);   // dock/undock enable
        ADD_FIELD32(dudpol,14,1);  // dock/undock polarity
        ADD_FIELD32(fphyrst,15,1); // force phy reset
        ADD_FIELD32(extlen,16,1);  // external link status enable
        ADD_FIELD32(rsvd,17,1);    // reserved
        ADD_FIELD32(sdp0d,18,1);   // software controlled pin data
        ADD_FIELD32(sdp1d,19,1);   // software controlled pin data
        ADD_FIELD32(sdp2d,20,1);   // software controlled pin data
        ADD_FIELD32(sdp3d,21,1);   // software controlled pin data
        ADD_FIELD32(sdp0i,22,1);   // software controlled pin dir
        ADD_FIELD32(sdp1i,23,1);   // software controlled pin dir
        ADD_FIELD32(sdp2i,24,1);   // software controlled pin dir
        ADD_FIELD32(sdp3i,25,1);   // software controlled pin dir
        ADD_FIELD32(rst,26,1);     // reset
        ADD_FIELD32(rfce,27,1);    // receive flow control enable
        ADD_FIELD32(tfce,28,1);    // transmit flow control enable
        ADD_FIELD32(rte,29,1);     // routing tag enable
        ADD_FIELD32(vme,30,1);     // vlan enable
        ADD_FIELD32(phyrst,31,1);  // phy reset
    };
    CTRL ctrl;

    struct STATUS : public Reg<uint32_t> { // 0x0008 STATUS Register
        using Reg<uint32_t>::operator=;
        ADD_FIELD32(fd,0,1);       // full duplex
        ADD_FIELD32(lu,1,1);       // link up
        ADD_FIELD32(func,2,2);     // function id
        ADD_FIELD32(txoff,4,1);    // transmission paused
        ADD_FIELD32(tbimode,5,1);  // tbi mode
        ADD_FIELD32(speed,6,2);    // link speed
        ADD_FIELD32(asdv,8,2);     // auto speed detection value
        ADD_FIELD32(mtxckok,10,1); // mtx clock running ok
        ADD_FIELD32(pci66,11,1);   // In 66Mhz pci slot
        ADD_FIELD32(bus64,12,1);   // in 64 bit slot
        ADD_FIELD32(pcix,13,1);    // Pci mode
        ADD_FIELD32(pcixspd,14,2); // pci x speed
    };
    STATUS sts;

    struct EECD : public Reg<uint32_t> { // 0x0010 EECD Register
        using Reg<uint32_t>::operator=;
        ADD_FIELD32(sk,0,1);       // clack input to the eeprom
        ADD_FIELD32(cs,1,1);       // chip select to eeprom
        ADD_FIELD32(din,2,1);      // data input to eeprom
        ADD_FIELD32(dout,3,1);     // data output bit
        ADD_FIELD32(fwe,4,2);      // flash write enable
        ADD_FIELD32(ee_req,6,1);   // request eeprom access
        ADD_FIELD32(ee_gnt,7,1);   // grant eeprom access
        ADD_FIELD32(ee_pres,8,1);  // eeprom present
        ADD_FIELD32(ee_size,9,1);  // eeprom size
        ADD_FIELD32(ee_sz1,10,1);  // eeprom size
        ADD_FIELD32(rsvd,11,2);    // reserved
        ADD_FIELD32(ee_type,13,1); // type of eeprom
    } ;
    EECD eecd;

    struct EERD : public Reg<uint32_t> { // 0x0014 EERD Register
        using Reg<uint32_t>::operator=;
        ADD_FIELD32(start,0,1);  // start read
        ADD_FIELD32(done,4,1);   // done read
        ADD_FIELD32(addr,8,8);   // address
        ADD_FIELD32(data,16,16); // data
    };
    EERD eerd;

    struct CTRL_EXT : public Reg<uint32_t> { // 0x0018 CTRL_EXT Register
        using Reg<uint32_t>::operator=;
        ADD_FIELD32(gpi_en,0,4);      // enable interrupts from gpio
        ADD_FIELD32(phyint,5,1);      // reads the phy internal int status
        ADD_FIELD32(sdp2_data,6,1);   // data from gpio sdp
        ADD_FIELD32(spd3_data,7,1);   // data frmo gpio sdp
        ADD_FIELD32(spd2_iodir,10,1); // direction of sdp2
        ADD_FIELD32(spd3_iodir,11,1); // direction of sdp2
        ADD_FIELD32(asdchk,12,1);     // initiate auto-speed-detection
        ADD_FIELD32(eerst,13,1);      // reset the eeprom
        ADD_FIELD32(spd_byps,15,1);   // bypass speed select
        ADD_FIELD32(ro_dis,17,1);     // disable relaxed memory ordering
        ADD_FIELD32(vreg,21,1);       // power down the voltage regulator
        ADD_FIELD32(link_mode,22,2);  // interface to talk to the link
        ADD_FIELD32(iame, 27,1);      // interrupt acknowledge auto-mask ??
        ADD_FIELD32(drv_loaded, 28,1);// driver is loaded and incharge of device
        ADD_FIELD32(timer_clr, 29,1); // clear interrupt timers after IMS clear ??
    };
    CTRL_EXT ctrl_ext;

    struct MDIC : public Reg<uint32_t> { // 0x0020 MDIC Register
        using Reg<uint32_t>::operator=;
        ADD_FIELD32(data,0,16);   // data
        ADD_FIELD32(regadd,16,5); // register address
        ADD_FIELD32(phyadd,21,5); // phy addresses
        ADD_FIELD32(op,26,2);     // opcode
        ADD_FIELD32(r,28,1);      // ready
        ADD_FIELD32(i,29,1);      // interrupt
        ADD_FIELD32(e,30,1);      // error
    };