ns_gige.cc

M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作为模拟平台

/*
 * Copyright (c) 2004, 2005
 * The Regents of The University of Michigan
 * All Rights Reserved
 *
 * This code is part of the M5 simulator.
 *
 * Permission is granted to use, copy, create derivative works and
 * redistribute this software and such derivative works for any
 * purpose, so long as the copyright notice above, this grant of
 * permission, and the disclaimer below appear in all copies made; and
 * so long as the name of The University of Michigan is not used in
 * any advertising or publicity pertaining to the use or distribution
 * of this software without specific, written prior authorization.
 *
 * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
 * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
 * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
 * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
 * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
 * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
 * DAMAGES.
 *
 * Authors: Nathan L. Binkert
 *          Lisa R. Hsu
 */

/** @file
 * Device module for modelling the National Semiconductor
 * DP83820 ethernet controller.  Does not support priority queueing
 */
#include <deque>
#include <string>

#include "base/inet.hh"
#include "cpu/thread_context.hh"
#include "dev/etherlink.hh"
#include "dev/ns_gige.hh"
#include "dev/pciconfigall.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/NSGigE.hh"
#include "sim/debug.hh"
#include "sim/host.hh"
#include "sim/stats.hh"
#include "sim/system.hh"

const char *NsRxStateStrings[] =
{
    "rxIdle",
    "rxDescRefr",
    "rxDescRead",
    "rxFifoBlock",
    "rxFragWrite",
    "rxDescWrite",
    "rxAdvance"
};

const char *NsTxStateStrings[] =
{
    "txIdle",
    "txDescRefr",
    "txDescRead",
    "txFifoBlock",
    "txFragRead",
    "txDescWrite",
    "txAdvance"
};

const char *NsDmaState[] =
{
    "dmaIdle",
    "dmaReading",
    "dmaWriting",
    "dmaReadWaiting",
    "dmaWriteWaiting"
};

using namespace std;
using namespace Net;
using namespace TheISA;

///////////////////////////////////////////////////////////////////////
//
// NSGigE PCI Device
//
NSGigE::NSGigE(Params *p)
    : EtherDevice(p), ioEnable(false),
      txFifo(p->tx_fifo_size), rxFifo(p->rx_fifo_size),
      txPacket(0), rxPacket(0), txPacketBufPtr(NULL), rxPacketBufPtr(NULL),
      txXferLen(0), rxXferLen(0), rxDmaFree(false), txDmaFree(false),
      clock(p->clock),
      txState(txIdle), txEnable(false), CTDD(false), txHalt(false),
      txFragPtr(0), txDescCnt(0), txDmaState(dmaIdle), rxState(rxIdle),
      rxEnable(false), CRDD(false), rxPktBytes(0), rxHalt(false),
      rxFragPtr(0), rxDescCnt(0), rxDmaState(dmaIdle), extstsEnable(false),
      eepromState(eepromStart), eepromClk(false), eepromBitsToRx(0),
      eepromOpcode(0), eepromAddress(0), eepromData(0),
      dmaReadDelay(p->dma_read_delay), dmaWriteDelay(p->dma_write_delay),
      dmaReadFactor(p->dma_read_factor), dmaWriteFactor(p->dma_write_factor),
      rxDmaData(NULL), rxDmaAddr(0), rxDmaLen(0),
      txDmaData(NULL), txDmaAddr(0), txDmaLen(0),
      rxDmaReadEvent(this), rxDmaWriteEvent(this),
      txDmaReadEvent(this), txDmaWriteEvent(this),
      dmaDescFree(p->dma_desc_free), dmaDataFree(p->dma_data_free),
      txDelay(p->tx_delay), rxDelay(p->rx_delay),
      rxKickTick(0), rxKickEvent(this), txKickTick(0), txKickEvent(this),
      txEvent(this), rxFilterEnable(p->rx_filter),
      acceptBroadcast(false), acceptMulticast(false), acceptUnicast(false),
      acceptPerfect(false), acceptArp(false), multicastHashEnable(false),
      intrDelay(p->intr_delay), intrTick(0), cpuPendingIntr(false),
      intrEvent(0), interface(0)
{


    interface = new NSGigEInt(name() + ".int0", this);

    regsReset();
    memcpy(&rom.perfectMatch, p->hardware_address.bytes(), ETH_ADDR_LEN);

    memset(&rxDesc32, 0, sizeof(rxDesc32));
    memset(&txDesc32, 0, sizeof(txDesc32));
    memset(&rxDesc64, 0, sizeof(rxDesc64));
    memset(&txDesc64, 0, sizeof(txDesc64));
}

NSGigE::~NSGigE()
{}

void
NSGigE::regStats()
{
    txBytes
        .name(name() + ".txBytes")
        .desc("Bytes Transmitted")
        .prereq(txBytes)
        ;

    rxBytes
        .name(name() + ".rxBytes")
        .desc("Bytes Received")
        .prereq(rxBytes)
        ;

    txPackets
        .name(name() + ".txPackets")
        .desc("Number of Packets Transmitted")
        .prereq(txBytes)
        ;

    rxPackets
        .name(name() + ".rxPackets")
        .desc("Number of Packets Received")
        .prereq(rxBytes)
        ;

    txIpChecksums
        .name(name() + ".txIpChecksums")
        .desc("Number of tx IP Checksums done by device")
        .precision(0)
        .prereq(txBytes)
        ;

    rxIpChecksums
        .name(name() + ".rxIpChecksums")
        .desc("Number of rx IP Checksums done by device")
        .precision(0)
        .prereq(rxBytes)
        ;

    txTcpChecksums
        .name(name() + ".txTcpChecksums")
        .desc("Number of tx TCP Checksums done by device")
        .precision(0)
        .prereq(txBytes)
        ;

    rxTcpChecksums
        .name(name() + ".rxTcpChecksums")
        .desc("Number of rx TCP Checksums done by device")
        .precision(0)
        .prereq(rxBytes)
        ;

    txUdpChecksums
        .name(name() + ".txUdpChecksums")
        .desc("Number of tx UDP Checksums done by device")
        .precision(0)
        .prereq(txBytes)
        ;

    rxUdpChecksums
        .name(name() + ".rxUdpChecksums")
        .desc("Number of rx UDP Checksums done by device")
        .precision(0)
        .prereq(rxBytes)
        ;

    descDmaReads
        .name(name() + ".descDMAReads")
        .desc("Number of descriptors the device read w/ DMA")
        .precision(0)
        ;

    descDmaWrites
        .name(name() + ".descDMAWrites")
        .desc("Number of descriptors the device wrote w/ DMA")
        .precision(0)
        ;

    descDmaRdBytes
        .name(name() + ".descDmaReadBytes")
        .desc("number of descriptor bytes read w/ DMA")
        .precision(0)
        ;

   descDmaWrBytes
        .name(name() + ".descDmaWriteBytes")
        .desc("number of descriptor bytes write w/ DMA")
        .precision(0)
        ;

    txBandwidth
        .name(name() + ".txBandwidth")
        .desc("Transmit Bandwidth (bits/s)")
        .precision(0)
        .prereq(txBytes)
        ;

    rxBandwidth
        .name(name() + ".rxBandwidth")
        .desc("Receive Bandwidth (bits/s)")
        .precision(0)
        .prereq(rxBytes)
        ;

    totBandwidth
        .name(name() + ".totBandwidth")
        .desc("Total Bandwidth (bits/s)")
        .precision(0)
        .prereq(totBytes)
        ;

    totPackets
        .name(name() + ".totPackets")
        .desc("Total Packets")
        .precision(0)
        .prereq(totBytes)
        ;

    totBytes
        .name(name() + ".totBytes")
        .desc("Total Bytes")
        .precision(0)
        .prereq(totBytes)
        ;

    totPacketRate
        .name(name() + ".totPPS")
        .desc("Total Tranmission Rate (packets/s)")
        .precision(0)
        .prereq(totBytes)
        ;

    txPacketRate
        .name(name() + ".txPPS")
        .desc("Packet Tranmission Rate (packets/s)")
        .precision(0)
        .prereq(txBytes)
        ;

    rxPacketRate
        .name(name() + ".rxPPS")
        .desc("Packet Reception Rate (packets/s)")
        .precision(0)
        .prereq(rxBytes)
        ;

    postedSwi
        .name(name() + ".postedSwi")
        .desc("number of software interrupts posted to CPU")
        .precision(0)
        ;

    totalSwi
        .name(name() + ".totalSwi")
        .desc("total number of Swi written to ISR")
        .precision(0)
        ;

    coalescedSwi
        .name(name() + ".coalescedSwi")
        .desc("average number of Swi's coalesced into each post")
        .precision(0)
        ;

    postedRxIdle
        .name(name() + ".postedRxIdle")
        .desc("number of rxIdle interrupts posted to CPU")
        .precision(0)
        ;

    totalRxIdle
        .name(name() + ".totalRxIdle")
        .desc("total number of RxIdle written to ISR")
        .precision(0)
        ;

    coalescedRxIdle
        .name(name() + ".coalescedRxIdle")
        .desc("average number of RxIdle's coalesced into each post")
        .precision(0)
        ;

    postedRxOk
        .name(name() + ".postedRxOk")
        .desc("number of RxOk interrupts posted to CPU")
        .precision(0)
        ;

    totalRxOk
        .name(name() + ".totalRxOk")
        .desc("total number of RxOk written to ISR")
        .precision(0)
        ;

    coalescedRxOk
        .name(name() + ".coalescedRxOk")
        .desc("average number of RxOk's coalesced into each post")
        .precision(0)
        ;

    postedRxDesc
        .name(name() + ".postedRxDesc")
        .desc("number of RxDesc interrupts posted to CPU")
        .precision(0)
        ;

    totalRxDesc
        .name(name() + ".totalRxDesc")
        .desc("total number of RxDesc written to ISR")
        .precision(0)
        ;

    coalescedRxDesc
        .name(name() + ".coalescedRxDesc")
        .desc("average number of RxDesc's coalesced into each post")
        .precision(0)
        ;

    postedTxOk
        .name(name() + ".postedTxOk")
        .desc("number of TxOk interrupts posted to CPU")
        .precision(0)
        ;

    totalTxOk
        .name(name() + ".totalTxOk")
        .desc("total number of TxOk written to ISR")
        .precision(0)
        ;

    coalescedTxOk
        .name(name() + ".coalescedTxOk")
        .desc("average number of TxOk's coalesced into each post")
        .precision(0)
        ;

    postedTxIdle
        .name(name() + ".postedTxIdle")
        .desc("number of TxIdle interrupts posted to CPU")
        .precision(0)
        ;

    totalTxIdle
        .name(name() + ".totalTxIdle")
        .desc("total number of TxIdle written to ISR")
        .precision(0)
        ;

    coalescedTxIdle
        .name(name() + ".coalescedTxIdle")
        .desc("average number of TxIdle's coalesced into each post")
        .precision(0)
        ;

    postedTxDesc
        .name(name() + ".postedTxDesc")
        .desc("number of TxDesc interrupts posted to CPU")
        .precision(0)
        ;

    totalTxDesc
        .name(name() + ".totalTxDesc")
        .desc("total number of TxDesc written to ISR")
        .precision(0)
        ;

    coalescedTxDesc
        .name(name() + ".coalescedTxDesc")
        .desc("average number of TxDesc's coalesced into each post")
        .precision(0)
        ;

    postedRxOrn
        .name(name() + ".postedRxOrn")
        .desc("number of RxOrn posted to CPU")
        .precision(0)
        ;

    totalRxOrn
        .name(name() + ".totalRxOrn")
        .desc("total number of RxOrn written to ISR")
        .precision(0)
        ;

    coalescedRxOrn
        .name(name() + ".coalescedRxOrn")
        .desc("average number of RxOrn's coalesced into each post")
        .precision(0)
        ;

    coalescedTotal
        .name(name() + ".coalescedTotal")
        .desc("average number of interrupts coalesced into each post")
        .precision(0)
        ;

    postedInterrupts
        .name(name() + ".postedInterrupts")
        .desc("number of posts to CPU")
        .precision(0)
        ;

    droppedPackets
        .name(name() + ".droppedPackets")
        .desc("number of packets dropped")
        .precision(0)
        ;

    coalescedSwi = totalSwi / postedInterrupts;
    coalescedRxIdle = totalRxIdle / postedInterrupts;
    coalescedRxOk = totalRxOk / postedInterrupts;
    coalescedRxDesc = totalRxDesc / postedInterrupts;
    coalescedTxOk = totalTxOk / postedInterrupts;
    coalescedTxIdle = totalTxIdle / postedInterrupts;
    coalescedTxDesc = totalTxDesc / postedInterrupts;
    coalescedRxOrn = totalRxOrn / postedInterrupts;

    coalescedTotal = (totalSwi + totalRxIdle + totalRxOk + totalRxDesc +
                      totalTxOk + totalTxIdle + totalTxDesc +
                      totalRxOrn) / postedInterrupts;

    txBandwidth = txBytes * Stats::constant(8) / simSeconds;
    rxBandwidth = rxBytes * Stats::constant(8) / simSeconds;
    totBandwidth = txBandwidth + rxBandwidth;
    totBytes = txBytes + rxBytes;
    totPackets = txPackets + rxPackets;

    txPacketRate = txPackets / simSeconds;
    rxPacketRate = rxPackets / simSeconds;
}