faults.cc

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· CC 代码 · 共 713 行 · 第 1/2 页

/*
 * Copyright (c) 2003, 2004, 2005
 * The Regents of The University of Michigan
 * All Rights Reserved
 *
 * This code is part of the M5 simulator.
 *
 * Permission is granted to use, copy, create derivative works and
 * redistribute this software and such derivative works for any
 * purpose, so long as the copyright notice above, this grant of
 * permission, and the disclaimer below appear in all copies made; and
 * so long as the name of The University of Michigan is not used in
 * any advertising or publicity pertaining to the use or distribution
 * of this software without specific, written prior authorization.
 *
 * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
 * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
 * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
 * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
 * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
 * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
 * DAMAGES.
 *
 * Authors: Gabe M. Black
 *          Kevin T. Lim
 */

#include <algorithm>

#include "arch/sparc/faults.hh"
#include "arch/sparc/isa_traits.hh"
#include "arch/sparc/types.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#if !FULL_SYSTEM
#include "arch/sparc/process.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
#endif

using namespace std;

namespace SparcISA
{

template<> SparcFaultBase::FaultVals
    SparcFault<PowerOnReset>::vals =
    {"power_on_reset", 0x001, 0, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<WatchDogReset>::vals =
    {"watch_dog_reset", 0x002, 120, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<ExternallyInitiatedReset>::vals =
    {"externally_initiated_reset", 0x003, 110, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<SoftwareInitiatedReset>::vals =
    {"software_initiated_reset", 0x004, 130, {SH, SH, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<REDStateException>::vals =
    {"RED_state_exception", 0x005, 1, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<StoreError>::vals =
    {"store_error", 0x007, 201, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<InstructionAccessException>::vals =
    {"instruction_access_exception", 0x008, 300, {H, H, H}};

//XXX This trap is apparently dropped from ua2005
/*template<> SparcFaultBase::FaultVals
    SparcFault<InstructionAccessMMUMiss>::vals =
    {"inst_mmu", 0x009, 2, {H, H, H}};*/

template<> SparcFaultBase::FaultVals
    SparcFault<InstructionAccessError>::vals =
    {"instruction_access_error", 0x00A, 400, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<IllegalInstruction>::vals =
    {"illegal_instruction", 0x010, 620, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<PrivilegedOpcode>::vals =
    {"privileged_opcode", 0x011, 700, {P, SH, SH}};

//XXX This trap is apparently dropped from ua2005
/*template<> SparcFaultBase::FaultVals
    SparcFault<UnimplementedLDD>::vals =
    {"unimp_ldd", 0x012, 6, {H, H, H}};*/

//XXX This trap is apparently dropped from ua2005
/*template<> SparcFaultBase::FaultVals
    SparcFault<UnimplementedSTD>::vals =
    {"unimp_std", 0x013, 6, {H, H, H}};*/

template<> SparcFaultBase::FaultVals
    SparcFault<FpDisabled>::vals =
    {"fp_disabled", 0x020, 800, {P, P, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<FpExceptionIEEE754>::vals =
    {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<FpExceptionOther>::vals =
    {"fp_exception_other", 0x022, 1110, {P, P, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<TagOverflow>::vals =
    {"tag_overflow", 0x023, 1400, {P, P, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<CleanWindow>::vals =
    {"clean_window", 0x024, 1010, {P, P, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<DivisionByZero>::vals =
    {"division_by_zero", 0x028, 1500, {P, P, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<InternalProcessorError>::vals =
    {"internal_processor_error", 0x029, 4, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<InstructionInvalidTSBEntry>::vals =
    {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}};

template<> SparcFaultBase::FaultVals
    SparcFault<DataInvalidTSBEntry>::vals =
    {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<DataAccessException>::vals =
    {"data_access_exception", 0x030, 1201, {H, H, H}};

//XXX This trap is apparently dropped from ua2005
/*template<> SparcFaultBase::FaultVals
    SparcFault<DataAccessMMUMiss>::vals =
    {"data_mmu", 0x031, 12, {H, H, H}};*/

template<> SparcFaultBase::FaultVals
    SparcFault<DataAccessError>::vals =
    {"data_access_error", 0x032, 1210, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<DataAccessProtection>::vals =
    {"data_access_protection", 0x033, 1207, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<MemAddressNotAligned>::vals =
    {"mem_address_not_aligned", 0x034, 1020, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<LDDFMemAddressNotAligned>::vals =
    {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<STDFMemAddressNotAligned>::vals =
    {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<PrivilegedAction>::vals =
    {"privileged_action", 0x037, 1110, {H, H, SH}};

template<> SparcFaultBase::FaultVals
    SparcFault<LDQFMemAddressNotAligned>::vals =
    {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<STQFMemAddressNotAligned>::vals =
    {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<InstructionRealTranslationMiss>::vals =
    {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}};

template<> SparcFaultBase::FaultVals
    SparcFault<DataRealTranslationMiss>::vals =
    {"data_real_translation_miss", 0x03F, 1203, {H, H, H}};

//XXX This trap is apparently dropped from ua2005
/*template<> SparcFaultBase::FaultVals
    SparcFault<AsyncDataError>::vals =
    {"async_data", 0x040, 2, {H, H, H}};*/

template<> SparcFaultBase::FaultVals
    SparcFault<InterruptLevelN>::vals =
    {"interrupt_level_n", 0x040, 0, {P, P, SH}};

template<> SparcFaultBase::FaultVals
    SparcFault<HstickMatch>::vals =
    {"hstick_match", 0x05E, 1601, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<TrapLevelZero>::vals =
    {"trap_level_zero", 0x05F, 202, {H, H, SH}};

template<> SparcFaultBase::FaultVals
    SparcFault<InterruptVector>::vals =
    {"interrupt_vector", 0x060, 2630, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<PAWatchpoint>::vals =
    {"PA_watchpoint", 0x061, 1209, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<VAWatchpoint>::vals =
    {"VA_watchpoint", 0x062, 1120, {P, P, SH}};

template<> SparcFaultBase::FaultVals
    SparcFault<FastInstructionAccessMMUMiss>::vals =
    {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}};

template<> SparcFaultBase::FaultVals
    SparcFault<FastDataAccessMMUMiss>::vals =
    {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<FastDataAccessProtection>::vals =
    {"fast_data_access_protection", 0x06C, 1207, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<InstructionBreakpoint>::vals =
    {"instruction_break", 0x076, 610, {H, H, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<CpuMondo>::vals =
    {"cpu_mondo", 0x07C, 1608, {P, P, SH}};

template<> SparcFaultBase::FaultVals
    SparcFault<DevMondo>::vals =
    {"dev_mondo", 0x07D, 1611, {P, P, SH}};

template<> SparcFaultBase::FaultVals
    SparcFault<ResumableError>::vals =
    {"resume_error", 0x07E, 3330, {P, P, SH}};

template<> SparcFaultBase::FaultVals
    SparcFault<SpillNNormal>::vals =
    {"spill_n_normal", 0x080, 900, {P, P, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<SpillNOther>::vals =
    {"spill_n_other", 0x0A0, 900, {P, P, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<FillNNormal>::vals =
    {"fill_n_normal", 0x0C0, 900, {P, P, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<FillNOther>::vals =
    {"fill_n_other", 0x0E0, 900, {P, P, H}};

template<> SparcFaultBase::FaultVals
    SparcFault<TrapInstruction>::vals =
    {"trap_instruction", 0x100, 1602, {P, P, H}};

/**
 * This causes the thread context to enter RED state. This causes the side
 * effects which go with entering RED state because of a trap.
 */

void enterREDState(ThreadContext *tc)
{
    //@todo Disable the mmu?
    //@todo Disable watchpoints?
    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
    //HPSTATE.red = 1
    HPSTATE |= (1 << 5);
    //HPSTATE.hpriv = 1
    HPSTATE |= (1 << 2);
    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
    //PSTATE.priv is set to 1 here. The manual says it should be 0, but
    //Legion sets it to 1.
    MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
    PSTATE |= (1 << 2);
    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
}

/**
 * This sets everything up for a RED state trap except for actually jumping to
 * the handler.
 */

void doREDFault(ThreadContext *tc, TrapType tt)
{
    MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
    MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
    MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
    //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
    MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
    MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
    MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
    //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
    MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
    MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
    MiscReg PC = tc->readPC();
    MiscReg NPC = tc->readNextPC();

    TL++;

    if (bits(PSTATE, 3,3)) {
        PC &= mask(32);
        NPC &= mask(32);
    }

    //set TSTATE.gl to gl
    replaceBits(TSTATE, 42, 40, GL);
    //set TSTATE.ccr to ccr
    replaceBits(TSTATE, 39, 32, CCR);
    //set TSTATE.asi to asi
    replaceBits(TSTATE, 31, 24, ASI);
    //set TSTATE.pstate to pstate
    replaceBits(TSTATE, 20, 8, PSTATE);
    //set TSTATE.cwp to cwp
    replaceBits(TSTATE, 4, 0, CWP);

    //Write back TSTATE
    tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);

    //set TPC to PC
    tc->setMiscRegNoEffect(MISCREG_TPC, PC);
    //set TNPC to NPC
    tc->setMiscRegNoEffect(MISCREG_TNPC, NPC);

    //set HTSTATE.hpstate to hpstate
    tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE);

    //TT = trap type;
    tc->setMiscRegNoEffect(MISCREG_TT, tt);

    //Update GL
    tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));

    PSTATE = mbits(PSTATE, 2, 2); // just save the priv bit
    PSTATE |= (1 << 4); //set PSTATE.pef to 1
    tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE);

    //set HPSTATE.red to 1
    HPSTATE |= (1 << 5);
    //set HPSTATE.hpriv to 1
    HPSTATE |= (1 << 2);
    //set HPSTATE.ibe to 0
    HPSTATE &= ~(1 << 10);