base.isa

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· ISA 代码 · 共 550 行 · 第 1/2 页

                    switch (reg - MaxMicroReg) {
                      case 1:
                        ccprintf(os, "%%y");
                        break;
                      case 2:
                        ccprintf(os, "%%ccr");
                        break;
                      case 3:
                        ccprintf(os, "%%cansave");
                        break;
                      case 4:
                        ccprintf(os, "%%canrestore");
                        break;
                      case 5:
                        ccprintf(os, "%%cleanwin");
                        break;
                      case 6:
                        ccprintf(os, "%%otherwin");
                        break;
                      case 7:
                        ccprintf(os, "%%wstate");
                        break;
                    }
                }
            } else if (reg < Ctrl_Base_DepTag) {
                ccprintf(os, "%%f%d", reg - FP_Base_DepTag);
            } else {
                switch (reg - Ctrl_Base_DepTag) {
                  case MISCREG_ASI:
                    ccprintf(os, "%%asi");
                    break;
                  case MISCREG_FPRS:
                    ccprintf(os, "%%fprs");
                    break;
                  case MISCREG_PCR:
                    ccprintf(os, "%%pcr");
                    break;
                  case MISCREG_PIC:
                    ccprintf(os, "%%pic");
                    break;
                  case MISCREG_GSR:
                    ccprintf(os, "%%gsr");
                    break;
                  case MISCREG_SOFTINT:
                    ccprintf(os, "%%softint");
                    break;
                  case MISCREG_SOFTINT_SET:
                    ccprintf(os, "%%softint_set");
                    break;
                  case MISCREG_SOFTINT_CLR:
                    ccprintf(os, "%%softint_clr");
                    break;
                  case MISCREG_TICK_CMPR:
                    ccprintf(os, "%%tick_cmpr");
                    break;
                  case MISCREG_STICK:
                    ccprintf(os, "%%stick");
                    break;
                  case MISCREG_STICK_CMPR:
                    ccprintf(os, "%%stick_cmpr");
                    break;
                  case MISCREG_TPC:
                    ccprintf(os, "%%tpc");
                    break;
                  case MISCREG_TNPC:
                    ccprintf(os, "%%tnpc");
                    break;
                  case MISCREG_TSTATE:
                    ccprintf(os, "%%tstate");
                    break;
                  case MISCREG_TT:
                    ccprintf(os, "%%tt");
                    break;
                  case MISCREG_TICK:
                    ccprintf(os, "%%tick");
                    break;
                  case MISCREG_TBA:
                    ccprintf(os, "%%tba");
                    break;
                  case MISCREG_PSTATE:
                    ccprintf(os, "%%pstate");
                    break;
                  case MISCREG_TL:
                    ccprintf(os, "%%tl");
                    break;
                  case MISCREG_PIL:
                    ccprintf(os, "%%pil");
                    break;
                  case MISCREG_CWP:
                    ccprintf(os, "%%cwp");
                    break;
                  case MISCREG_GL:
                    ccprintf(os, "%%gl");
                    break;
                  case MISCREG_HPSTATE:
                    ccprintf(os, "%%hpstate");
                    break;
                  case MISCREG_HTSTATE:
                    ccprintf(os, "%%htstate");
                    break;
                  case MISCREG_HINTP:
                    ccprintf(os, "%%hintp");
                    break;
                  case MISCREG_HTBA:
                    ccprintf(os, "%%htba");
                    break;
                  case MISCREG_HSTICK_CMPR:
                    ccprintf(os, "%%hstick_cmpr");
                    break;
                  case MISCREG_HVER:
                    ccprintf(os, "%%hver");
                    break;
                  case MISCREG_STRAND_STS_REG:
                    ccprintf(os, "%%strand_sts_reg");
                    break;
                  case MISCREG_FSR:
                    ccprintf(os, "%%fsr");
                    break;
                  default:
                    ccprintf(os, "%%ctrl%d", reg - Ctrl_Base_DepTag);
                }
            }
        }

        std::string SparcStaticInst::generateDisassembly(Addr pc,
            const SymbolTable *symtab) const
        {
            std::stringstream ss;

            printMnemonic(ss, mnemonic);

            // just print the first two source regs... if there's
            // a third one, it's a read-modify-write dest (Rc),
            // e.g. for CMOVxx
            if(_numSrcRegs > 0)
            {
                printReg(ss, _srcRegIdx[0]);
            }
            if(_numSrcRegs > 1)
            {
                ss << ",";
                printReg(ss, _srcRegIdx[1]);
            }

            // just print the first dest... if there's a second one,
            // it's generally implicit
            if(_numDestRegs > 0)
            {
                if(_numSrcRegs > 0)
                    ss << ",";
                    printReg(ss, _destRegIdx[0]);
            }

            return ss.str();
        }

        bool passesFpCondition(uint32_t fcc, uint32_t condition)
        {
            bool u = (fcc == 3);
            bool g = (fcc == 2);
            bool l = (fcc == 1);
            bool e = (fcc == 0);
            switch(condition)
            {
              case FAlways:
                return 1;
              case FNever:
                return 0;
              case FUnordered:
                return u;
              case FGreater:
                return g;
              case FUnorderedOrGreater:
                return u || g;
              case FLess:
                return l;
              case FUnorderedOrLess:
                return u || l;
              case FLessOrGreater:
                return l || g;
              case FNotEqual:
                return l || g || u;
              case FEqual:
                return e;
              case FUnorderedOrEqual:
                return u || e;
              case FGreaterOrEqual:
                return g || e;
              case FUnorderedOrGreaterOrEqual:
                return u || g || e;
              case FLessOrEqual:
                return l || e;
              case FUnorderedOrLessOrEqual:
                return u || l || e;
              case FOrdered:
                return e || l || g;
            }
            panic("Tried testing condition nonexistant "
                    "condition code %d", condition);
        }

        bool passesCondition(uint32_t codes, uint32_t condition)
        {
            CondCodes condCodes;
            condCodes.bits =  0;
            condCodes.c = codes & 0x1 ? 1 : 0;
            condCodes.v = codes & 0x2 ? 1 : 0;
            condCodes.z = codes & 0x4 ? 1 : 0;
            condCodes.n = codes & 0x8 ? 1 : 0;

            switch(condition)
            {
              case Always:
                return true;
              case Never:
                return false;
              case NotEqual:
                return !condCodes.z;
              case Equal:
                return condCodes.z;
              case Greater:
                return !(condCodes.z | (condCodes.n ^ condCodes.v));
              case LessOrEqual:
                return condCodes.z | (condCodes.n ^ condCodes.v);
              case GreaterOrEqual:
                return !(condCodes.n ^ condCodes.v);
              case Less:
                return (condCodes.n ^ condCodes.v);
              case GreaterUnsigned:
                return !(condCodes.c | condCodes.z);
              case LessOrEqualUnsigned:
                return (condCodes.c | condCodes.z);
              case CarryClear:
                return !condCodes.c;
              case CarrySet:
                return condCodes.c;
              case Positive:
                return !condCodes.n;
              case Negative:
                return condCodes.n;
              case OverflowClear:
                return !condCodes.v;
              case OverflowSet:
                return condCodes.v;
            }
            panic("Tried testing condition nonexistant "
                    "condition code %d", condition);
        }
}};

output exec {{
    /// Check "FP enabled" machine status bit.  Called when executing any FP
    /// instruction in full-system mode.
    /// @retval Full-system mode: NoFault if FP is enabled, FpDisabled
    /// if not.  Non-full-system mode: always returns NoFault.
#if FULL_SYSTEM
    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
    {
        Fault fault = NoFault;	// dummy... this ipr access should not fault
        if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef &&
            xc->readMiscReg(MISCREG_FPRS) & 0x4)
            return NoFault;
        else
            return new FpDisabled;
    }
#else
    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
    {
        return NoFault;
    }
#endif
}};