decoder.isa

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· ISA 代码 · 共 1,399 行 · 第 1/5 页

                                Frd.udw = lsbX;
                                break;
                            default:
                                uint64_t msbShift = Gsr<2:0> * 8;
                                uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
                                uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
                                uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
                                Frd.udw = ((msbX & msbMask) << msbShift) |
                                        ((lsbX & lsbMask) >> lsbShift);
                        }
                }});
                0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
                0x4C: FailUnimpl::bshuffle();
                0x4D: FailUnimpl::fexpand();
                0x50: FailUnimpl::fpadd16();
                0x51: FailUnimpl::fpadd16s();
                0x52: FailUnimpl::fpadd32();
                0x53: FailUnimpl::fpadd32s();
                0x54: FailUnimpl::fpsub16();
                0x55: FailUnimpl::fpsub16s();
                0x56: FailUnimpl::fpsub32();
                0x57: FailUnimpl::fpsub32s();
                0x60: FpBasic::fzero({{Frd.df = 0;}});
                0x61: FpBasic::fzeros({{Frds.sf = 0;}});
                0x62: FailUnimpl::fnor();
                0x63: FailUnimpl::fnors();
                0x64: FailUnimpl::fandnot2();
                0x65: FailUnimpl::fandnot2s();
                0x66: FpBasic::fnot2({{
                        Frd.df = (double)(~((uint64_t)Frs2.df));
                }});
                0x67: FpBasic::fnot2s({{
                        Frds.sf = (float)(~((uint32_t)Frs2s.sf));
                }});
                0x68: FailUnimpl::fandnot1();
                0x69: FailUnimpl::fandnot1s();
                0x6A: FpBasic::fnot1({{
                        Frd.df = (double)(~((uint64_t)Frs1.df));
                }});
                0x6B: FpBasic::fnot1s({{
                        Frds.sf = (float)(~((uint32_t)Frs1s.sf));
                }});
                0x6C: FailUnimpl::fxor();
                0x6D: FailUnimpl::fxors();
                0x6E: FailUnimpl::fnand();
                0x6F: FailUnimpl::fnands();
                0x70: FailUnimpl::fand();
                0x71: FailUnimpl::fands();
                0x72: FailUnimpl::fxnor();
                0x73: FailUnimpl::fxnors();
                0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}});
                0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}});
                0x76: FailUnimpl::fornot2();
                0x77: FailUnimpl::fornot2s();
                0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}});
                0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}});
                0x7A: FailUnimpl::fornot1();
                0x7B: FailUnimpl::fornot1s();
                0x7C: FailUnimpl::for();
                0x7D: FailUnimpl::fors();
                0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}});
                0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}});
                0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
                0x81: FailUnimpl::siam();
            }
            // M5 special opcodes use the reserved IMPDEP2A opcode space
            0x37: decode M5FUNC {
#if FULL_SYSTEM
                format BasicOperate {
                    // we have 7 bits of space here to play with...
                    0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0);
                                  }}, No_OpClass, IsNonSpeculative);
                    0x50: m5readfile({{
                                     O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2);
                                     }}, IsNonSpeculative);
                    0x51: m5break({{PseudoInst::debugbreak(xc->tcBase());
                                  }}, IsNonSpeculative);
                    0x54: m5panic({{
                                  panic("M5 panic instruction called at pc=%#x.", xc->readPC());
                                  }}, No_OpClass, IsNonSpeculative);
                }
#endif
                default: Trap::impdep2({{fault = new IllegalInstruction;}});
            }
            0x38: Branch::jmpl({{
                Addr target = Rs1 + Rs2_or_imm13;
                if(target & 0x3)
                    fault = new MemAddressNotAligned;
                else
                {
                    if (Pstate<3:>)
                        Rd = (xc->readPC())<31:0>;
                    else
                        Rd = xc->readPC();
                    NNPC = target;
                }
            }});
            0x39: Branch::return({{
                Addr target = Rs1 + Rs2_or_imm13;
                if(fault == NoFault)
                {
                    //Check for fills which are higher priority than alignment
                    //faults.
                    if(Canrestore == 0)
                    {
                        if(Otherwin)
                            fault = new FillNOther(4*Wstate<5:3>);
                        else
                            fault = new FillNNormal(4*Wstate<2:0>);
                    }
                    //Check for alignment faults
                    else if(target & 0x3)
                        fault = new MemAddressNotAligned;
                    else
                    {
                        NNPC = target;
                        Cwp = (Cwp - 1 + NWindows) % NWindows;
                        Cansave = Cansave + 1;
                        Canrestore = Canrestore - 1;
                    }
                }
            }});
            0x3A: decode CC
            {
                0x0: Trap::tcci({{
                    if(passesCondition(Ccr<3:0>, COND2))
                    {
                        int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
                        DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
                        fault = new TrapInstruction(lTrapNum);
                    }
                }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
                0x2: Trap::tccx({{
                    if(passesCondition(Ccr<7:4>, COND2))
                    {
                        int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
                        DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
                        fault = new TrapInstruction(lTrapNum);
                    }
                }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
            }
            0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier,
                          MemWriteOp);
            0x3C: save({{
                if(Cansave == 0)
                {
                    if(Otherwin)
                        fault = new SpillNOther(4*Wstate<5:3>);
                    else
                        fault = new SpillNNormal(4*Wstate<2:0>);
                }
                else if(Cleanwin - Canrestore == 0)
                {
                    fault = new CleanWindow;
                }
                else
                {
                    Cwp = (Cwp + 1) % NWindows;
                    Rd_next = Rs1 + Rs2_or_imm13;
                    Cansave = Cansave - 1;
                    Canrestore = Canrestore + 1;
                }
            }});
            0x3D: restore({{
                if(Canrestore == 0)
                {
                    if(Otherwin)
                        fault = new FillNOther(4*Wstate<5:3>);
                    else
                        fault = new FillNNormal(4*Wstate<2:0>);
                }
                else
                {
                    Cwp = (Cwp - 1 + NWindows) % NWindows;
                    Rd_prev = Rs1 + Rs2_or_imm13;
                    Cansave = Cansave + 1;
                    Canrestore = Canrestore - 1;
                }
            }});
            0x3E: decode FCN {
                0x0: Priv::done({{
                    Cwp = Tstate<4:0>;
                    Pstate = Tstate<20:8>;
                    Asi = Tstate<31:24>;
                    Ccr = Tstate<39:32>;
                    Gl = Tstate<42:40>;
                    Hpstate = Htstate;
                    NPC = Tnpc;
                    NNPC = Tnpc + 4;
                    Tl = Tl - 1;
                }}, checkTl=true);
                0x1: Priv::retry({{
                    Cwp = Tstate<4:0>;
                    Pstate = Tstate<20:8>;
                    Asi = Tstate<31:24>;
                    Ccr = Tstate<39:32>;
                    Gl = Tstate<42:40>;
                    Hpstate = Htstate;
                    NPC = Tpc;
                    NNPC = Tnpc;
                    Tl = Tl - 1;
                }}, checkTl=true);
            }
        }
    }
    0x3: decode OP3 {
        format Load {
            0x00: lduw({{Rd = Mem.uw;}});
            0x01: ldub({{Rd = Mem.ub;}});
            0x02: lduh({{Rd = Mem.uhw;}});
            0x03: ldtw({{
                        RdLow = (Mem.tuw).a;
                        RdHigh = (Mem.tuw).b;
            }});
        }
        format Store {
            0x04: stw({{Mem.uw = Rd.sw;}});
            0x05: stb({{Mem.ub = Rd.sb;}});
            0x06: sth({{Mem.uhw = Rd.shw;}});
            0x07: sttw({{
                      //This temporary needs to be here so that the parser
                      //will correctly identify this instruction as a store.
                      //It's probably either the parenthesis or referencing
                      //the member variable that throws confuses it.
                      Twin32_t temp;
                      temp.a = RdLow<31:0>;
                      temp.b = RdHigh<31:0>;
                      Mem.tuw = temp;
                  }});
        }
        format Load {
            0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
            0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
            0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
            0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
        }
        0x0D: Swap::ldstub({{Mem.ub = 0xFF;}},
                           {{
                               uint8_t tmp = mem_data;
                               Rd.ub = tmp;
                           }}, MEM_SWAP);
        0x0E: Store::stx({{Mem.udw = Rd}});
        0x0F: Swap::swap({{Mem.uw = Rd.uw}},
                         {{
                               uint32_t tmp = mem_data;
                               Rd.uw = tmp;
                         }}, MEM_SWAP);
        format LoadAlt {
            0x10: lduwa({{Rd = Mem.uw;}});
            0x11: lduba({{Rd = Mem.ub;}});
            0x12: lduha({{Rd = Mem.uhw;}});
            0x13: decode EXT_ASI {
                //ASI_LDTD_AIUP
                0x22: TwinLoad::ldtx_aiup(
                    {{RdLow.udw = (Mem.tudw).a;
                      RdHigh.udw = (Mem.tudw).b;}});
                //ASI_LDTD_AIUS
                0x23: TwinLoad::ldtx_aius(
                    {{RdLow.udw = (Mem.tudw).a;
                      RdHigh.udw = (Mem.tudw).b;}});
                //ASI_QUAD_LDD
                0x24: TwinLoad::ldtx_quad_ldd(
                    {{RdLow.udw = (Mem.tudw).a;
                      RdHigh.udw = (Mem.tudw).b;}});
                //ASI_LDTX_REAL
                0x26: TwinLoad::ldtx_real(
                    {{RdLow.udw = (Mem.tudw).a;
                      RdHigh.udw = (Mem.tudw).b;}});
                //ASI_LDTX_N
                0x27: TwinLoad::ldtx_n(
                    {{RdLow.udw = (Mem.tudw).a;
                      RdHigh.udw = (Mem.tudw).b;}});
                //ASI_LDTX_AIUP_L
                0x2A: TwinLoad::ldtx_aiup_l(
                    {{RdLow.udw = (Mem.tudw).a;
                      RdHigh.udw = (Mem.tudw).b;}});
                //ASI_LDTX_AIUS_L
                0x2B: TwinLoad::ldtx_aius_l(
                    {{RdLow.udw = (Mem.tudw).a;
                      RdHigh.udw = (Mem.tudw).b;}});