decoder.isa

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· ISA 代码 · 共 1,399 行 · 第 1/5 页

                    0x01: fmovs_fcc0({{
                        if(passesFpCondition(Fsr<11:10>, COND4))
                            Frds = Frs2s;
                        else
                            Frds = Frds;
                    }});
                    0x02: fmovd_fcc0({{
                        if(passesFpCondition(Fsr<11:10>, COND4))
                            Frd = Frs2;
                        else
                            Frd = Frd;
                    }});
                    0x03: FpUnimpl::fmovq_fcc0();
                    0x25: fmovrsz({{
                        if(Rs1 == 0)
                            Frds = Frs2s;
                        else
                            Frds = Frds;
                    }});
                    0x26: fmovrdz({{
                        if(Rs1 == 0)
                            Frd = Frs2;
                        else
                            Frd = Frd;
                    }});
                    0x27: FpUnimpl::fmovrqz();
                    0x41: fmovs_fcc1({{
                        if(passesFpCondition(Fsr<33:32>, COND4))
                            Frds = Frs2s;
                        else
                            Frds = Frds;
                    }});
                    0x42: fmovd_fcc1({{
                        if(passesFpCondition(Fsr<33:32>, COND4))
                            Frd = Frs2;
                        else
                            Frd = Frd;
                    }});
                    0x43: FpUnimpl::fmovq_fcc1();
                    0x45: fmovrslez({{
                        if(Rs1 <= 0)
                            Frds = Frs2s;
                        else
                            Frds = Frds;
                    }});
                    0x46: fmovrdlez({{
                        if(Rs1 <= 0)
                            Frd = Frs2;
                        else
                            Frd = Frd;
                    }});
                    0x47: FpUnimpl::fmovrqlez();
                    0x51: fcmps({{
                          uint8_t fcc;
                          if(isnan(Frs1s) || isnan(Frs2s))
                              fcc = 3;
                          else if(Frs1s < Frs2s)
                              fcc = 1;
                          else if(Frs1s > Frs2s)
                              fcc = 2;
                          else
                              fcc = 0;
                          uint8_t firstbit = 10;
                          if(FCMPCC)
                              firstbit = FCMPCC * 2 + 30;
                          Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
                    }});
                    0x52: fcmpd({{
                          uint8_t fcc;
                          if(isnan(Frs1) || isnan(Frs2))
                              fcc = 3;
                          else if(Frs1 < Frs2)
                              fcc = 1;
                          else if(Frs1 > Frs2)
                              fcc = 2;
                          else
                              fcc = 0;
                          uint8_t firstbit = 10;
                          if(FCMPCC)
                              firstbit = FCMPCC * 2 + 30;
                          Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
                    }});
                    0x53: FpUnimpl::fcmpq();
                    0x55: fcmpes({{
                          uint8_t fcc = 0;
                          if(isnan(Frs1s) || isnan(Frs2s))
                              fault = new FpExceptionIEEE754;
                          if(Frs1s < Frs2s)
                              fcc = 1;
                          else if(Frs1s > Frs2s)
                              fcc = 2;
                          uint8_t firstbit = 10;
                          if(FCMPCC)
                              firstbit = FCMPCC * 2 + 30;
                          Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
                    }});
                    0x56: fcmped({{
                          uint8_t fcc = 0;
                          if(isnan(Frs1) || isnan(Frs2))
                              fault = new FpExceptionIEEE754;
                          if(Frs1 < Frs2)
                              fcc = 1;
                          else if(Frs1 > Frs2)
                              fcc = 2;
                          uint8_t firstbit = 10;
                          if(FCMPCC)
                              firstbit = FCMPCC * 2 + 30;
                          Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
                    }});
                    0x57: FpUnimpl::fcmpeq();
                    0x65: fmovrslz({{
                        if(Rs1 < 0)
                            Frds = Frs2s;
                        else
                            Frds = Frds;
                    }});
                    0x66: fmovrdlz({{
                        if(Rs1 < 0)
                            Frd = Frs2;
                        else
                            Frd = Frd;
                    }});
                    0x67: FpUnimpl::fmovrqlz();
                    0x81: fmovs_fcc2({{
                        if(passesFpCondition(Fsr<35:34>, COND4))
                            Frds = Frs2s;
                        else
                            Frds = Frds;
                    }});
                    0x82: fmovd_fcc2({{
                        if(passesFpCondition(Fsr<35:34>, COND4))
                            Frd = Frs2;
                        else
                            Frd = Frd;
                    }});
                    0x83: FpUnimpl::fmovq_fcc2();
                    0xA5: fmovrsnz({{
                        if(Rs1 != 0)
                            Frds = Frs2s;
                        else
                            Frds = Frds;
                    }});
                    0xA6: fmovrdnz({{
                        if(Rs1 != 0)
                            Frd = Frs2;
                        else
                            Frd = Frd;
                    }});
                    0xA7: FpUnimpl::fmovrqnz();
                    0xC1: fmovs_fcc3({{
                        if(passesFpCondition(Fsr<37:36>, COND4))
                            Frds = Frs2s;
                        else
                            Frds = Frds;
                    }});
                    0xC2: fmovd_fcc3({{
                        if(passesFpCondition(Fsr<37:36>, COND4))
                            Frd = Frs2;
                        else
                            Frd = Frd;
                    }});
                    0xC3: FpUnimpl::fmovq_fcc3();
                    0xC5: fmovrsgz({{
                        if(Rs1 > 0)
                            Frds = Frs2s;
                        else
                            Frds = Frds;
                    }});
                    0xC6: fmovrdgz({{
                        if(Rs1 > 0)
                            Frd = Frs2;
                        else
                            Frd = Frd;
                    }});
                    0xC7: FpUnimpl::fmovrqgz();
                    0xE5: fmovrsgez({{
                        if(Rs1 >= 0)
                            Frds = Frs2s;
                        else
                            Frds = Frds;
                    }});
                    0xE6: fmovrdgez({{
                        if(Rs1 >= 0)
                            Frd = Frs2;
                        else
                            Frd = Frd;
                    }});
                    0xE7: FpUnimpl::fmovrqgez();
                    0x101: fmovs_icc({{
                        if(passesCondition(Ccr<3:0>, COND4))
                            Frds = Frs2s;
                        else
                            Frds = Frds;
                    }});
                    0x102: fmovd_icc({{
                        if(passesCondition(Ccr<3:0>, COND4))
                            Frd = Frs2;
                        else
                            Frd = Frd;
                    }});
                    0x103: FpUnimpl::fmovq_icc();
                    0x181: fmovs_xcc({{
                        if(passesCondition(Ccr<7:4>, COND4))
                            Frds = Frs2s;
                        else
                            Frds = Frds;
                    }});
                    0x182: fmovd_xcc({{
                        if(passesCondition(Ccr<7:4>, COND4))
                            Frd = Frs2;
                        else
                            Frd = Frd;
                    }});
                    0x183: FpUnimpl::fmovq_xcc();
                    default: FailUnimpl::fpop2();
                }
            }
            //This used to be just impdep1, but now it's a whole bunch
            //of instructions
            0x36: decode OPF{
                0x00: FailUnimpl::edge8();
                0x01: FailUnimpl::edge8n();
                0x02: FailUnimpl::edge8l();
                0x03: FailUnimpl::edge8ln();
                0x04: FailUnimpl::edge16();
                0x05: FailUnimpl::edge16n();
                0x06: FailUnimpl::edge16l();
                0x07: FailUnimpl::edge16ln();
                0x08: FailUnimpl::edge32();
                0x09: FailUnimpl::edge32n();
                0x0A: FailUnimpl::edge32l();
                0x0B: FailUnimpl::edge32ln();
                0x10: FailUnimpl::array8();
                0x12: FailUnimpl::array16();
                0x14: FailUnimpl::array32();
                0x18: BasicOperate::alignaddr({{
                    uint64_t sum = Rs1 + Rs2;
                    Rd = sum & ~7;
                    Gsr = (Gsr & ~7) | (sum & 7);
                }});
                0x19: FailUnimpl::bmask();
                0x1A: BasicOperate::alignaddresslittle({{
                    uint64_t sum = Rs1 + Rs2;
                    Rd = sum & ~7;
                    Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
                }});
                0x20: FailUnimpl::fcmple16();
                0x22: FailUnimpl::fcmpne16();
                0x24: FailUnimpl::fcmple32();
                0x26: FailUnimpl::fcmpne32();
                0x28: FailUnimpl::fcmpgt16();
                0x2A: FailUnimpl::fcmpeq16();
                0x2C: FailUnimpl::fcmpgt32();
                0x2E: FailUnimpl::fcmpeq32();
                0x31: FailUnimpl::fmul8x16();
                0x33: FailUnimpl::fmul8x16au();
                0x35: FailUnimpl::fmul8x16al();
                0x36: FailUnimpl::fmul8sux16();
                0x37: FailUnimpl::fmul8ulx16();
                0x38: FailUnimpl::fmuld8sux16();
                0x39: FailUnimpl::fmuld8ulx16();
                0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
                0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
                0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
                0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
                0x48: BasicOperate::faligndata({{
                        uint64_t msbX = Frs1.udw;
                        uint64_t lsbX = Frs2.udw;
                        //Some special cases need to be split out, first
                        //because they're the most likely to be used, and
                        //second because otherwise, we end up shifting by
                        //greater than the width of the type being shifted,
                        //namely 64, which produces undefined results according
                        //to the C standard.
                        switch(Gsr<2:0>)
                        {
                            case 0:
                                Frd.udw = msbX;
                                break;
                            case 8: