pal.isa

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· ISA 代码 · 共 279 行

// -*- mode:c++ -*-

//Copyright (c) 2003, 2004, 2005
//The Regents of The University of Michigan
//All Rights Reserved

//This code is part of the M5 simulator.

//Permission is granted to use, copy, create derivative works and
//redistribute this software and such derivative works for any purpose,
//so long as the copyright notice above, this grant of permission, and
//the disclaimer below appear in all copies made; and so long as the
//name of The University of Michigan is not used in any advertising or
//publicity pertaining to the use or distribution of this software
//without specific, written prior authorization.

//THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
//UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
//WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
//IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
//MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
//THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
//INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
//DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
//WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
//ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

//Authors: Steven K. Reinhardt

////////////////////////////////////////////////////////////////////
//
// PAL calls & PAL-specific instructions
//

output header {{
    /**
     * Base class for emulated call_pal calls (used only in
     * non-full-system mode).
     */
    class EmulatedCallPal : public AlphaStaticInst
    {
      protected:

        /// Constructor.
        EmulatedCallPal(const char *mnem, ExtMachInst _machInst,
                        OpClass __opClass)
            : AlphaStaticInst(mnem, _machInst, __opClass)
        {
        }

        std::string
        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };
}};

output decoder {{
    std::string
    EmulatedCallPal::generateDisassembly(Addr pc,
                                         const SymbolTable *symtab) const
    {
#ifdef SS_COMPATIBLE_DISASSEMBLY
        return csprintf("%s %s", "call_pal", mnemonic);
#else
        return csprintf("%-10s %s", "call_pal", mnemonic);
#endif
    }
}};

def format EmulatedCallPal(code, *flags) {{
    iop = InstObjParams(name, Name, 'EmulatedCallPal', code, flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = BasicExecute.subst(iop)
}};

output header {{
    /**
     * Base class for full-system-mode call_pal instructions.
     * Probably could turn this into a leaf class and get rid of the
     * parser template.
     */
    class CallPalBase : public AlphaStaticInst
    {
      protected:
        int palFunc;	///< Function code part of instruction
        int palOffset;	///< Target PC, offset from IPR_PAL_BASE
        bool palValid;	///< is the function code valid?
        bool palPriv;	///< is this call privileged?

        /// Constructor.
        CallPalBase(const char *mnem, ExtMachInst _machInst,
                    OpClass __opClass);

        std::string
        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };
}};

output decoder {{
    inline
    CallPalBase::CallPalBase(const char *mnem, ExtMachInst _machInst,
                             OpClass __opClass)
        : AlphaStaticInst(mnem, _machInst, __opClass),
        palFunc(PALFUNC)
    {
        // From the 21164 HRM (paraphrased):
        // Bit 7 of the function code (mask 0x80) indicates
        // whether the call is privileged (bit 7 == 0) or
        // unprivileged (bit 7 == 1).  The privileged call table
        // starts at 0x2000, the unprivielged call table starts at
        // 0x3000.  Bits 5-0 (mask 0x3f) are used to calculate the
        // offset.
        const int palPrivMask = 0x80;
        const int palOffsetMask = 0x3f;

        // Pal call is invalid unless all other bits are 0
        palValid = ((machInst & ~(palPrivMask | palOffsetMask)) == 0);
        palPriv = ((machInst & palPrivMask) == 0);
        int shortPalFunc = (machInst & palOffsetMask);
        // Add 1 to base to set pal-mode bit
        palOffset = (palPriv ? 0x2001 : 0x3001) + (shortPalFunc << 6);
    }

    std::string
    CallPalBase::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
        return csprintf("%-10s %#x", "call_pal", palFunc);
    }
}};

def format CallPal(code, *flags) {{
    iop = InstObjParams(name, Name, 'CallPalBase', code, flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = BasicExecute.subst(iop)
}};

////////////////////////////////////////////////////////////////////
//
// hw_ld, hw_st
//

output header {{
    /**
     * Base class for hw_ld and hw_st.
     */
    class HwLoadStore : public Memory
    {
      protected:

        /// Displacement for EA calculation (signed).
        int16_t disp;

        /// Constructor
        HwLoadStore(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                    StaticInstPtr _eaCompPtr = nullStaticInstPtr,
                    StaticInstPtr _memAccPtr = nullStaticInstPtr);

        std::string
        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };
}};


output decoder {{
    inline
    HwLoadStore::HwLoadStore(const char *mnem, ExtMachInst _machInst,
                             OpClass __opClass,
                             StaticInstPtr _eaCompPtr,
                             StaticInstPtr _memAccPtr)
        : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
        disp(HW_LDST_DISP)
    {
        memAccessFlags = 0;
        if (HW_LDST_PHYS) memAccessFlags |= PHYSICAL;
        if (HW_LDST_ALT)  memAccessFlags |= ALTMODE;
        if (HW_LDST_VPTE) memAccessFlags |= VPTE;
        if (HW_LDST_LOCK) memAccessFlags |= LOCKED;
    }

    std::string
    HwLoadStore::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
#ifdef SS_COMPATIBLE_DISASSEMBLY
        return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB);
#else
        // HW_LDST_LOCK and HW_LDST_COND are the same bit.
        const char *lock_str =
            (HW_LDST_LOCK) ? (flags[IsLoad] ? ",LOCK" : ",COND") : "";

        return csprintf("%-10s r%d,%d(r%d)%s%s%s%s%s",
                        mnemonic, RA, disp, RB,
                        HW_LDST_PHYS ? ",PHYS" : "",
                        HW_LDST_ALT ? ",ALT" : "",
                        HW_LDST_QUAD ? ",QUAD" : "",
                        HW_LDST_VPTE ? ",VPTE" : "",
                        lock_str);
#endif
    }
}};

def format HwLoad(ea_code, memacc_code, class_ext, *flags) {{
    (header_output, decoder_output, decode_block, exec_output) = \
        LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
                      mem_flags = [], inst_flags = flags,
                      base_class = 'HwLoadStore', exec_template_base = 'Load')
}};


def format HwStore(ea_code, memacc_code, class_ext, *flags) {{
    (header_output, decoder_output, decode_block, exec_output) = \
        LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
                      mem_flags = [], inst_flags = flags,
                      base_class = 'HwLoadStore', exec_template_base = 'Store')
}};


def format HwStoreCond(ea_code, memacc_code, postacc_code, class_ext,
                       *flags) {{
    (header_output, decoder_output, decode_block, exec_output) = \
        LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
                      postacc_code, mem_flags = [], inst_flags = flags,
                      base_class = 'HwLoadStore')
}};


output header {{
    /**
     * Base class for hw_mfpr and hw_mtpr.
     */
    class HwMoveIPR : public AlphaStaticInst
    {
      protected:
        /// Index of internal processor register.
        int ipr_index;

        /// Constructor
        HwMoveIPR(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
            : AlphaStaticInst(mnem, _machInst, __opClass),
              ipr_index(HW_IPR_IDX)
        {
        }

        std::string
        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };
}};

output decoder {{
    std::string
    HwMoveIPR::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
        if (_numSrcRegs > 0) {
            // must be mtpr
            return csprintf("%-10s r%d,IPR(%#x)",
                            mnemonic, RA, ipr_index);
        }
        else {
            // must be mfpr
            return csprintf("%-10s IPR(%#x),r%d",
                            mnemonic, ipr_index, RA);
        }
    }
}};

def format HwMoveIPR(code, *flags) {{
    all_flags = ['IprAccessOp']
    all_flags += flags
    iop = InstObjParams(name, Name, 'HwMoveIPR', code, all_flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = BasicExecute.subst(iop)
}};