decoder.isa

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· ISA 代码 · 共 861 行 · 第 1/3 页

    0x17: decode FP_FULLFUNC {
        format BasicOperateWithNopCheck {
            0x010: cvtlq({{
                Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
            }});
            0x030: cvtql({{
                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
            }});

            // We treat the precise & imprecise trapping versions of
            // cvtql identically.
            0x130, 0x530: cvtqlv({{
                // To avoid overflow, all the upper 32 bits must match
                // the sign bit of the lower 32.  We code this as
                // checking the upper 33 bits for all 0s or all 1s.
                uint64_t sign_bits = Fb.uq<63:31>;
                if (sign_bits != 0 && sign_bits != mask(33))
                    fault = new IntegerOverflowFault;
                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
            }});

            0x020: cpys({{  // copy sign
                Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
            }});
            0x021: cpysn({{ // copy sign negated
                Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
            }});
            0x022: cpyse({{ // copy sign and exponent
                Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
            }});

            0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
            0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
            0x02c: fcmovlt({{ Fc = (Fa <  0) ? Fb : Fc; }});
            0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
            0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
            0x02f: fcmovgt({{ Fc = (Fa >  0) ? Fb : Fc; }});

            0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
            0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
        }
    }

    // miscellaneous mem-format ops
    0x18: decode MEMFUNC {
        format WarnUnimpl {
            0x8000: fetch();
            0xa000: fetch_m();
            0xe800: ecb();
        }

        format MiscPrefetch {
            0xf800: wh64({{ EA = Rb & ~ULL(63); }},
                         {{ xc->writeHint(EA, 64, memAccessFlags); }},
                         mem_flags = NO_FAULT,
                         inst_flags = [IsMemRef, IsDataPrefetch,
                                       IsStore, MemWriteOp]);
        }

        format BasicOperate {
            0xc000: rpcc({{
#if FULL_SYSTEM
        /* Rb is a fake dependency so here is a fun way to get
         * the parser to understand that.
         */
                Ra = xc->readMiscReg(AlphaISA::IPR_CC) + (Rb & 0);

#else
                Ra = curTick;
#endif
            }}, IsUnverifiable);

            // All of the barrier instructions below do nothing in
            // their execute() methods (hence the empty code blocks).
            // All of their functionality is hard-coded in the
            // pipeline based on the flags IsSerializing,
            // IsMemBarrier, and IsWriteBarrier.  In the current
            // detailed CPU model, the execute() function only gets
            // called at fetch, so there's no way to generate pipeline
            // behavior at any other stage.  Once we go to an
            // exec-in-exec CPU model we should be able to get rid of
            // these flags and implement this behavior via the
            // execute() methods.

            // trapb is just a barrier on integer traps, where excb is
            // a barrier on integer and FP traps.  "EXCB is thus a
            // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
            // them the same though.
            0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
            0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
            0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
            0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
        }

#if FULL_SYSTEM
        format BasicOperate {
            0xe000: rc({{
                Ra = IntrFlag;
                IntrFlag = 0;
            }}, IsNonSpeculative, IsUnverifiable);
            0xf000: rs({{
                Ra = IntrFlag;
                IntrFlag = 1;
            }}, IsNonSpeculative, IsUnverifiable);
        }
#else
        format FailUnimpl {
            0xe000: rc();
            0xf000: rs();
        }
#endif
    }

#if FULL_SYSTEM
    0x00: CallPal::call_pal({{
        if (!palValid ||
            (palPriv
             && xc->readMiscReg(AlphaISA::IPR_ICM) != AlphaISA::mode_kernel)) {
            // invalid pal function code, or attempt to do privileged
            // PAL call in non-kernel mode
            fault = new UnimplementedOpcodeFault;
        }
        else {
            // check to see if simulator wants to do something special
            // on this PAL call (including maybe suppress it)
            bool dopal = xc->simPalCheck(palFunc);

            if (dopal) {
                xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, NPC);
                NPC = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + palOffset;
            }
        }
    }}, IsNonSpeculative);
#else
    0x00: decode PALFUNC {
        format EmulatedCallPal {
            0x00: halt ({{
                exitSimLoop("halt instruction encountered");
            }}, IsNonSpeculative);
            0x83: callsys({{
                xc->syscall(R0);
            }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
            // Read uniq reg into ABI return value register (r0)
            0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
            // Write uniq reg with value from ABI arg register (r16)
            0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
        }
    }
#endif

#if FULL_SYSTEM
    0x1b: decode PALMODE {
        0: OpcdecFault::hw_st_quad();
        1: decode HW_LDST_QUAD {
            format HwLoad {
                0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }},
                         L, IsSerializing, IsSerializeBefore);
                1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }},
                         Q, IsSerializing, IsSerializeBefore);
            }
        }
    }

    0x1f: decode PALMODE {
        0: OpcdecFault::hw_st_cond();
        format HwStore {
            1: decode HW_LDST_COND {
                0: decode HW_LDST_QUAD {
                    0: hw_st({{ EA = (Rb + disp) & ~3; }},
                {{ Mem.ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore);
                    1: hw_st({{ EA = (Rb + disp) & ~7; }},
                {{ Mem.uq = Ra.uq; }}, Q, IsSerializing, IsSerializeBefore);
                }

                1: FailUnimpl::hw_st_cond();
            }
        }
    }

    0x19: decode PALMODE {
        0: OpcdecFault::hw_mfpr();
        format HwMoveIPR {
            1: hw_mfpr({{
                int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
                        IprToMiscRegIndex[ipr_index] : -1;
                if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) ||
                    miscRegIndex >= NumInternalProcRegs)
                        fault = new UnimplementedOpcodeFault;
                else
                    Ra = xc->readMiscReg(miscRegIndex);
            }}, IsIprAccess);
        }
    }

    0x1d: decode PALMODE {
        0: OpcdecFault::hw_mtpr();
        format HwMoveIPR {
            1: hw_mtpr({{
                int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
                        IprToMiscRegIndex[ipr_index] : -1;
                if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) ||
                    miscRegIndex >= NumInternalProcRegs)
                        fault = new UnimplementedOpcodeFault;
                else
                    xc->setMiscReg(miscRegIndex, Ra);
                if (traceData) { traceData->setData(Ra); }
            }}, IsIprAccess);
        }
    }

    format BasicOperate {
        0x1e: decode PALMODE {
            0: OpcdecFault::hw_rei();
            1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
        }

        // M5 special opcodes use the reserved 0x01 opcode space
        0x01: decode M5FUNC {
            0x00: arm({{
                PseudoInst::arm(xc->tcBase());
            }}, IsNonSpeculative);
            0x01: quiesce({{
                PseudoInst::quiesce(xc->tcBase());
            }}, IsNonSpeculative, IsQuiesce);
            0x02: quiesceNs({{
                PseudoInst::quiesceNs(xc->tcBase(), R16);
            }}, IsNonSpeculative, IsQuiesce);
            0x03: quiesceCycles({{
                PseudoInst::quiesceCycles(xc->tcBase(), R16);
            }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
            0x04: quiesceTime({{
                R0 = PseudoInst::quiesceTime(xc->tcBase());
            }}, IsNonSpeculative, IsUnverifiable);
            0x10: ivlb({{
                warn_once("Obsolete M5 instruction ivlb encountered.\n");
            }});
            0x11: ivle({{
                warn_once("Obsolete M5 instruction ivlb encountered.\n");
            }});
            0x20: m5exit_old({{
                PseudoInst::m5exit_old(xc->tcBase());
            }}, No_OpClass, IsNonSpeculative);
            0x21: m5exit({{
                PseudoInst::m5exit(xc->tcBase(), R16);
            }}, No_OpClass, IsNonSpeculative);
            0x31: loadsymbol({{
                PseudoInst::loadsymbol(xc->tcBase());
            }}, No_OpClass, IsNonSpeculative);
            0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }});
            0x40: resetstats({{
                PseudoInst::resetstats(xc->tcBase(), R16, R17);
            }}, IsNonSpeculative);
            0x41: dumpstats({{
                PseudoInst::dumpstats(xc->tcBase(), R16, R17);
            }}, IsNonSpeculative);
            0x42: dumpresetstats({{
                PseudoInst::dumpresetstats(xc->tcBase(), R16, R17);
            }}, IsNonSpeculative);
            0x43: m5checkpoint({{
                PseudoInst::m5checkpoint(xc->tcBase(), R16, R17);
            }}, IsNonSpeculative);
            0x50: m5readfile({{
                R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18);
            }}, IsNonSpeculative);
            0x51: m5break({{
                PseudoInst::debugbreak(xc->tcBase());
            }}, IsNonSpeculative);
            0x52: m5switchcpu({{
                PseudoInst::switchcpu(xc->tcBase());
            }}, IsNonSpeculative);
            0x53: m5addsymbol({{
                PseudoInst::addsymbol(xc->tcBase(), R16, R17);
            }}, IsNonSpeculative);
            0x54: m5panic({{
                panic("M5 panic instruction called at pc=%#x.", xc->readPC());
            }}, IsNonSpeculative);
            0x55: m5anBegin({{
                PseudoInst::anBegin(xc->tcBase(), R16);
            }}, IsNonSpeculative);
            0x56: m5anWait({{
                PseudoInst::anWait(xc->tcBase(), R16, R17);
            }}, IsNonSpeculative);
        }
    }
#endif
}