decoder.isa

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· ISA 代码 · 共 861 行 · 第 1/3 页

// -*- mode:c++ -*-

//Copyright (c) 2003, 2004, 2005, 2006
//The Regents of The University of Michigan
//All Rights Reserved

//This code is part of the M5 simulator.

//Permission is granted to use, copy, create derivative works and
//redistribute this software and such derivative works for any purpose,
//so long as the copyright notice above, this grant of permission, and
//the disclaimer below appear in all copies made; and so long as the
//name of The University of Michigan is not used in any advertising or
//publicity pertaining to the use or distribution of this software
//without specific, written prior authorization.

//THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
//UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
//WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
//IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
//MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
//THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
//INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
//DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
//WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
//ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

//Authors: Steven K. Reinhardt

////////////////////////////////////////////////////////////////////
//
// The actual decoder specification
//

decode OPCODE default Unknown::unknown() {

    format LoadAddress {
        0x08: lda({{ Ra = Rb + disp; }});
        0x09: ldah({{ Ra = Rb + (disp << 16); }});
    }

    format LoadOrNop {
        0x0a: ldbu({{ Ra.uq = Mem.ub; }});
        0x0c: ldwu({{ Ra.uq = Mem.uw; }});
        0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
        0x23: ldt({{ Fa = Mem.df; }});
        0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED);
        0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED);
#ifdef USE_COPY
        0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
                                      {{ fault = xc->copySrcTranslate(EA); }},
                                      inst_flags = [IsMemRef, IsLoad, IsCopy]);
#endif
    }

    format LoadOrPrefetch {
        0x28: ldl({{ Ra.sl = Mem.sl; }});
        0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT);
        // IsFloating flag on lds gets the prefetch to disassemble
        // using f31 instead of r31... funcitonally it's unnecessary
        0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }},
                  pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
    }

    format Store {
        0x0e: stb({{ Mem.ub = Ra<7:0>; }});
        0x0d: stw({{ Mem.uw = Ra<15:0>; }});
        0x2c: stl({{ Mem.ul = Ra<31:0>; }});
        0x2d: stq({{ Mem.uq = Ra.uq; }});
        0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
        0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
        0x27: stt({{ Mem.df = Fa; }});
#ifdef USE_COPY
        0x24: MiscPrefetch::copy_store({{ EA = Rb; }},
                                       {{ fault = xc->copy(EA); }},
                                       inst_flags = [IsMemRef, IsStore, IsCopy]);
#endif
    }

    format StoreCond {
        0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
                    {{
                        uint64_t tmp = write_result;
                        // see stq_c
                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
                        if (tmp == 1) {
                            xc->setStCondFailures(0);
                        }
                    }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
        0x2f: stq_c({{ Mem.uq = Ra; }},
                    {{
                        uint64_t tmp = write_result;
                        // If the write operation returns 0 or 1, then
                        // this was a conventional store conditional,
                        // and the value indicates the success/failure
                        // of the operation.  If another value is
                        // returned, then this was a Turbolaser
                        // mailbox access, and we don't update the
                        // result register at all.
                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
                        if (tmp == 1) {
                            // clear failure counter... this is
                            // non-architectural and for debugging
                            // only.
                            xc->setStCondFailures(0);
                        }
                    }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
    }

    format IntegerOperate {

        0x10: decode INTFUNC {	// integer arithmetic operations

            0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
            0x40: addlv({{
                uint32_t tmp  = Ra.sl + Rb_or_imm.sl;
                // signed overflow occurs when operands have same sign
                // and sign of result does not match.
                if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
                    fault = new IntegerOverflowFault;
                Rc.sl = tmp;
            }});
            0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
            0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});

            0x20: addq({{ Rc = Ra + Rb_or_imm; }});
            0x60: addqv({{
                uint64_t tmp = Ra + Rb_or_imm;
                // signed overflow occurs when operands have same sign
                // and sign of result does not match.
                if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
                    fault = new IntegerOverflowFault;
                Rc = tmp;
            }});
            0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
            0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});

            0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
            0x49: sublv({{
                uint32_t tmp  = Ra.sl - Rb_or_imm.sl;
                // signed overflow detection is same as for add,
                // except we need to look at the *complemented*
                // sign bit of the subtrahend (Rb), i.e., if the initial
                // signs are the *same* then no overflow can occur
                if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
                    fault = new IntegerOverflowFault;
                Rc.sl = tmp;
            }});
            0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
            0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});

            0x29: subq({{ Rc = Ra - Rb_or_imm; }});
            0x69: subqv({{
                uint64_t tmp  = Ra - Rb_or_imm;
                // signed overflow detection is same as for add,
                // except we need to look at the *complemented*
                // sign bit of the subtrahend (Rb), i.e., if the initial
                // signs are the *same* then no overflow can occur
                if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
                    fault = new IntegerOverflowFault;
                Rc = tmp;
            }});
            0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
            0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});

            0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
            0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
            0x4d: cmplt({{ Rc = (Ra.sq <  Rb_or_imm.sq); }});
            0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
            0x1d: cmpult({{ Rc = (Ra.uq <  Rb_or_imm.uq); }});

            0x0f: cmpbge({{
                int hi = 7;
                int lo = 0;
                uint64_t tmp = 0;
                for (int i = 0; i < 8; ++i) {
                    tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
                    hi += 8;
                    lo += 8;
                }
                Rc = tmp;
            }});
        }

        0x11: decode INTFUNC {	// integer logical operations

            0x00: and({{ Rc = Ra & Rb_or_imm; }});
            0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
            0x20: bis({{ Rc = Ra | Rb_or_imm; }});
            0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
            0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
            0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});

            // conditional moves
            0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
            0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
            0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
            0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
            0x44: cmovlt({{ Rc = (Ra.sq <  0) ? Rb_or_imm : Rc; }});
            0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
            0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
            0x66: cmovgt({{ Rc = (Ra.sq >  0) ? Rb_or_imm : Rc; }});

            // For AMASK, RA must be R31.
            0x61: decode RA {
                31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
            }

            // For IMPLVER, RA must be R31 and the B operand
            // must be the immediate value 1.
            0x6c: decode RA {
                31: decode IMM {
                    1: decode INTIMM {
                        // return EV5 for FULL_SYSTEM and EV6 otherwise
                        1: implver({{
#if FULL_SYSTEM
                             Rc = 1;
#else
                             Rc = 2;
#endif
                        }});
                    }
                }
            }

#if FULL_SYSTEM
            // The mysterious 11.25...
            0x25: WarnUnimpl::eleven25();
#endif
        }

        0x12: decode INTFUNC {
            0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
            0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
            0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});

            0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
            0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
            0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
            0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});

            0x52: mskwh({{
                int bv = Rb_or_imm<2:0>;
                Rc =  bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
            }});
            0x62: msklh({{
                int bv = Rb_or_imm<2:0>;
                Rc =  bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
            }});
            0x72: mskqh({{
                int bv = Rb_or_imm<2:0>;
                Rc =  bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
            }});

            0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
            0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
            0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
            0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});

            0x5a: extwh({{
                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
            0x6a: extlh({{
                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
            0x7a: extqh({{
                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});

            0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
            0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
            0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
            0x3b: insql({{ Rc = Ra       << (Rb_or_imm<2:0> * 8); }});

            0x57: inswh({{
                int bv = Rb_or_imm<2:0>;
                Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
            }});
            0x67: inslh({{
                int bv = Rb_or_imm<2:0>;
                Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
            }});
            0x77: insqh({{
                int bv = Rb_or_imm<2:0>;
                Rc = bv ? (Ra.uq       >> (64 - 8 * bv)) : 0;
            }});

            0x30: zap({{
                uint64_t zapmask = 0;
                for (int i = 0; i < 8; ++i) {