mem.isa

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· ISA 代码 · 共 773 行 · 第 1/2 页

// -*- mode:c++ -*-

//Copyright (c) 2003, 2004, 2005
//The Regents of The University of Michigan
//All Rights Reserved

//This code is part of the M5 simulator.

//Permission is granted to use, copy, create derivative works and
//redistribute this software and such derivative works for any purpose,
//so long as the copyright notice above, this grant of permission, and
//the disclaimer below appear in all copies made; and so long as the
//name of The University of Michigan is not used in any advertising or
//publicity pertaining to the use or distribution of this software
//without specific, written prior authorization.

//THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
//UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
//WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
//IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
//MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
//THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
//INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
//DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
//WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
//ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

//Authors: Steven K. Reinhardt
//         Kevin T. Lim

////////////////////////////////////////////////////////////////////
//
// Memory-format instructions: LoadAddress, Load, Store
//

output header {{
    /**
     * Base class for general Alpha memory-format instructions.
     */
    class Memory : public AlphaStaticInst
    {
      protected:

        /// Memory request flags.  See mem_req_base.hh.
        unsigned memAccessFlags;
        /// Pointer to EAComp object.
        const StaticInstPtr eaCompPtr;
        /// Pointer to MemAcc object.
        const StaticInstPtr memAccPtr;

        /// Constructor
        Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
               StaticInstPtr _eaCompPtr = nullStaticInstPtr,
               StaticInstPtr _memAccPtr = nullStaticInstPtr)
            : AlphaStaticInst(mnem, _machInst, __opClass),
              memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr)
        {
        }

        std::string
        generateDisassembly(Addr pc, const SymbolTable *symtab) const;

      public:

        const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
        const StaticInstPtr &memAccInst() const { return memAccPtr; }
    };

    /**
     * Base class for memory-format instructions using a 32-bit
     * displacement (i.e. most of them).
     */
    class MemoryDisp32 : public Memory
    {
      protected:
        /// Displacement for EA calculation (signed).
        int32_t disp;

        /// Constructor.
        MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                     StaticInstPtr _eaCompPtr = nullStaticInstPtr,
                     StaticInstPtr _memAccPtr = nullStaticInstPtr)
            : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
              disp(MEMDISP)
        {
        }
    };


    /**
     * Base class for a few miscellaneous memory-format insts
     * that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
     * None of these instructions has a destination register either.
     */
    class MemoryNoDisp : public Memory
    {
      protected:
        /// Constructor
        MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                     StaticInstPtr _eaCompPtr = nullStaticInstPtr,
                     StaticInstPtr _memAccPtr = nullStaticInstPtr)
            : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
        {
        }

        std::string
        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };
}};


output decoder {{
    std::string
    Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
        return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
                        flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
    }

    std::string
    MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
        return csprintf("%-10s (r%d)", mnemonic, RB);
    }
}};

def format LoadAddress(code) {{
    iop = InstObjParams(name, Name, 'MemoryDisp32', code)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = BasicExecute.subst(iop)
}};


def template LoadStoreDeclare {{
    /**
     * Static instruction class for "%(mnemonic)s".
     */
    class %(class_name)s : public %(base_class)s
    {
      protected:

        /**
         * "Fake" effective address computation class for "%(mnemonic)s".
         */
        class EAComp : public %(base_class)s
        {
          public:
            /// Constructor
            EAComp(ExtMachInst machInst);

            %(BasicExecDeclare)s
        };

        /**
         * "Fake" memory access instruction class for "%(mnemonic)s".
         */
        class MemAcc : public %(base_class)s
        {
          public:
            /// Constructor
            MemAcc(ExtMachInst machInst);

            %(BasicExecDeclare)s
        };

      public:

        /// Constructor.
        %(class_name)s(ExtMachInst machInst);

        %(BasicExecDeclare)s

        %(InitiateAccDeclare)s

        %(CompleteAccDeclare)s
    };
}};


def template InitiateAccDeclare {{
    Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};


def template CompleteAccDeclare {{
    Fault completeAcc(PacketPtr, %(CPU_exec_context)s *,
                      Trace::InstRecord *) const;
}};


def template EACompConstructor {{
    /** TODO: change op_class to AddrGenOp or something (requires
     * creating new member of OpClass enum in op_class.hh, updating
     * config files, etc.). */
    inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst)
        : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
    {
        %(constructor)s;
    }
}};


def template MemAccConstructor {{
    inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst)
        : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
    {
        %(constructor)s;
    }
}};


def template LoadStoreConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                          new EAComp(machInst), new MemAcc(machInst))
    {
        %(constructor)s;
    }
}};


def template EACompExecute {{
    Fault
    %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
    {
        Addr EA;
        Fault fault = NoFault;

        %(fp_enable_check)s;
        %(op_decl)s;
        %(op_rd)s;
        %(ea_code)s;

        if (fault == NoFault) {
            %(op_wb)s;
            xc->setEA(EA);
        }

        return fault;
    }
}};

def template LoadMemAccExecute {{
    Fault
    %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
    {
        Addr EA;
        Fault fault = NoFault;

        %(fp_enable_check)s;
        %(op_decl)s;
        %(op_rd)s;
        EA = xc->getEA();

        if (fault == NoFault) {
            fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
            %(memacc_code)s;
        }

        if (fault == NoFault) {
            %(op_wb)s;
        }

        return fault;
    }
}};


def template LoadExecute {{
    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                  Trace::InstRecord *traceData) const
    {
        Addr EA;
        Fault fault = NoFault;

        %(fp_enable_check)s;
        %(op_decl)s;
        %(op_rd)s;
        %(ea_code)s;

        if (fault == NoFault) {
            fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
            %(memacc_code)s;
        }

        if (fault == NoFault) {
            %(op_wb)s;
        }

        return fault;
    }
}};


def template LoadInitiateAcc {{
    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
                                      Trace::InstRecord *traceData) const
    {
        Addr EA;
        Fault fault = NoFault;

        %(fp_enable_check)s;
        %(op_src_decl)s;
        %(op_rd)s;
        %(ea_code)s;

        if (fault == NoFault) {
            fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
        }

        return fault;
    }
}};


def template LoadCompleteAcc {{
    Fault %(class_name)s::completeAcc(PacketPtr pkt,
                                      %(CPU_exec_context)s *xc,
                                      Trace::InstRecord *traceData) const
    {
        Fault fault = NoFault;

        %(fp_enable_check)s;
        %(op_decl)s;

        Mem = pkt->get<typeof(Mem)>();

        if (fault == NoFault) {
            %(memacc_code)s;
        }

        if (fault == NoFault) {
            %(op_wb)s;
        }

        return fault;
    }
}};


def template StoreMemAccExecute {{
    Fault
    %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
    {
        Addr EA;
        Fault fault = NoFault;

        %(fp_enable_check)s;
        %(op_decl)s;
        %(op_rd)s;
        EA = xc->getEA();

        if (fault == NoFault) {
            %(memacc_code)s;
        }

        if (fault == NoFault) {
            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
                              memAccessFlags, NULL);
            if (traceData) { traceData->setData(Mem); }
        }

        if (fault == NoFault) {
            %(postacc_code)s;
        }

        if (fault == NoFault) {
            %(op_wb)s;
        }

        return fault;
    }
}};

def template StoreCondMemAccExecute {{
    Fault
    %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
    {
        Addr EA;
        Fault fault = NoFault;
        uint64_t write_result = 0;