sconscript

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 代码 · 共 128 行

# -*- mode:python -*-

# Copyright (c) 2006
# The Regents of The University of Michigan
# All Rights Reserved
#
# This code is part of the M5 simulator.
#
# Permission is granted to use, copy, create derivative works and
# redistribute this software and such derivative works for any
# purpose, so long as the copyright notice above, this grant of
# permission, and the disclaimer below appear in all copies made; and
# so long as the name of The University of Michigan is not used in any
# advertising or publicity pertaining to the use or distribution of
# this software without specific, written prior authorization.
#
# THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
# UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
# WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
# EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
# LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
# INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
# ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
# IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
# DAMAGES.
#
# Authors: Steven K. Reinhardt

import sys

Import('*')

#################################################################
#
# ISA "switch header" generation.
#
# Auto-generate arch headers that include the right ISA-specific
# header based on the setting of THE_ISA preprocessor variable.
#
#################################################################

# List of headers to generate
isa_switch_hdrs = Split('''
        arguments.hh
        faults.hh
        interrupts.hh
        isa_traits.hh
        kernel_stats.hh
        locked_mem.hh
        mmaped_ipr.hh
        process.hh
        predecoder.hh
        regfile.hh
        remote_gdb.hh
        stacktrace.hh
        syscallreturn.hh
        tlb.hh
        types.hh
        utility.hh
        vtophys.hh
        ''')

# Set up this directory to support switching headers
make_switching_dir('arch', isa_switch_hdrs, env)

#################################################################
#
# Include architecture-specific files.
#
#################################################################

#
# Build a SCons scanner for ISA files
#
import SCons.Scanner

isa_scanner = SCons.Scanner.Classic("ISAScan",
                                    [".isa", ".ISA"],
                                    "SRCDIR",
                                    r'^\s*##include\s+"([\w/.-]*)"')

env.Append(SCANNERS = isa_scanner)

#
# Now create a Builder object that uses isa_parser.py to generate C++
# output from the ISA description (*.isa) files.
#

# Convert to File node to fix path
isa_parser = File('isa_parser.py')
cpu_models_file = File('../cpu/cpu_models.py')

# This sucks in the defintions of the CpuModel objects.
execfile(cpu_models_file.srcnode().abspath)

# Several files are generated from the ISA description.
# We always get the basic decoder and header file.
isa_desc_gen_files = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ]
# We also get an execute file for each selected CPU model.
isa_desc_gen_files += [CpuModel.dict[cpu].filename
                       for cpu in env['CPU_MODELS']]

# Also include the CheckerCPU as one of the models if it is being
# enabled via command line.
if env['USE_CHECKER']:
    isa_desc_gen_files += [CpuModel.dict['CheckerCPU'].filename]

# The emitter patches up the sources & targets to include the
# autogenerated files as targets and isa parser itself as a source.
def isa_desc_emitter(target, source, env):
    return (isa_desc_gen_files, [isa_parser, cpu_models_file] + source)

# Pieces are in place, so create the builder.
python = sys.executable  # use same Python binary used to run scons

# Also include the CheckerCPU as one of the models if it is being
# enabled via command line.
if env['USE_CHECKER']:
    isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS CheckerCPU',
                               emitter = isa_desc_emitter)
else:
    isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS',
                               emitter = isa_desc_emitter)

env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })