faults.cc

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· CC 代码 · 共 554 行 · 第 1/2 页

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void StoreAddressErrorFault::invoke(ThreadContext *tc)
{
  DPRINTF(MipsPRA,"%s encountered.\n", name());
  setExceptionState(tc,0x5);
  tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);

  // Set new PC
  Addr HandlerBase;
  HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
  setHandlerPC(HandlerBase,tc);
  //      warn("Exception Handler At: %x \n",HandlerBase);
  //      warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));

}

void TrapFault::invoke(ThreadContext *tc)
{
  DPRINTF(MipsPRA,"%s encountered.\n", name());
  //  warn("%s encountered.\n", name());
  setExceptionState(tc,0xD);

  // Set new PC
  Addr HandlerBase;
  HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
  setHandlerPC(HandlerBase,tc);
  //      warn("Exception Handler At: %x \n",HandlerBase);
  //      warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));
}

void BreakpointFault::invoke(ThreadContext *tc)
{
      setExceptionState(tc,0x9);

      // Set new PC
      Addr HandlerBase;
      HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
      setHandlerPC(HandlerBase,tc);
      //      warn("Exception Handler At: %x \n",HandlerBase);
      //      warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));

}

void DtbInvalidFault::invoke(ThreadContext *tc)
{
  DPRINTF(MipsPRA,"%s encountered.\n", name());
  //    warn("%s encountered.\n", name());
  tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);
  MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
  replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
  replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
  replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
  tc->setMiscRegNoEffect(MipsISA::EntryHi,eh);
  MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
  replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
  tc->setMiscRegNoEffect(MipsISA::Context,ctxt);
  setExceptionState(tc,0x3);


  // Set new PC
  Addr HandlerBase;
  HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
  setHandlerPC(HandlerBase,tc);
  //      warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));
}

void AddressErrorFault::invoke(ThreadContext *tc)
{
  DPRINTF(MipsPRA,"%s encountered.\n", name());
      setExceptionState(tc,0x4);
      tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);

      // Set new PC
      Addr HandlerBase;
      HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
      setHandlerPC(HandlerBase,tc);
}

void ItbInvalidFault::invoke(ThreadContext *tc)
{
  DPRINTF(MipsPRA,"%s encountered.\n", name());
      setExceptionState(tc,0x2);
      tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);
      MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
      replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
      replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
      replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
      tc->setMiscRegNoEffect(MipsISA::EntryHi,eh);
      MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
      replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
      tc->setMiscRegNoEffect(MipsISA::Context,ctxt);


      // Set new PC
      Addr HandlerBase;
      HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
      setHandlerPC(HandlerBase,tc);
      DPRINTF(MipsPRA,"Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));
}

void ItbRefillFault::invoke(ThreadContext *tc)
{
  DPRINTF(MipsPRA,"%s encountered (%x).\n", name(),BadVAddr);
  Addr HandlerBase;
  tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);
  MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
  replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
  replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
  replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
  tc->setMiscRegNoEffect(MipsISA::EntryHi,eh);
  MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
  replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
  tc->setMiscRegNoEffect(MipsISA::Context,ctxt);

  MiscReg stat = tc->readMiscReg(MipsISA::Status);
  // Since handler depends on EXL bit, must check EXL bit before setting it!!
  if(bits(stat,Status_EXL)==1){ // See MIPS ARM Vol 3, Revision 2, Page 38
    HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
  }else{
    HandlerBase = tc->readMiscReg(MipsISA::EBase); // Offset 0x000
  }

  setExceptionState(tc,0x2);
  setHandlerPC(HandlerBase,tc);
}

void DtbRefillFault::invoke(ThreadContext *tc)
{
  // Set new PC
  DPRINTF(MipsPRA,"%s encountered.\n", name());
  Addr HandlerBase;
  tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);
  MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
  replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
  replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
  replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
  tc->setMiscRegNoEffect(MipsISA::EntryHi,eh);
  MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
  replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
  tc->setMiscRegNoEffect(MipsISA::Context,ctxt);

  MiscReg stat = tc->readMiscReg(MipsISA::Status);
  // Since handler depends on EXL bit, must check EXL bit before setting it!!
  if(bits(stat,Status_EXL)==1){ // See MIPS ARM Vol 3, Revision 2, Page 38
    HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
  }else{
    HandlerBase = tc->readMiscReg(MipsISA::EBase); // Offset 0x000
  }


  setExceptionState(tc,0x3);

  setHandlerPC(HandlerBase,tc);
}

void TLBModifiedFault::invoke(ThreadContext *tc)
{
  DPRINTF(MipsPRA,"%s encountered.\n", name());
  tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);
  MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
  replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
  replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
  replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
  tc->setMiscRegNoEffect(MipsISA::EntryHi,eh);
  MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
  replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
  tc->setMiscRegNoEffect(MipsISA::Context,ctxt);

    // Set new PC
      Addr HandlerBase;
      HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
      setExceptionState(tc,0x1);
      setHandlerPC(HandlerBase,tc);
      //      warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));

}

void SystemCallFault::invoke(ThreadContext *tc)
{
  DPRINTF(MipsPRA,"%s encountered.\n", name());
      setExceptionState(tc,0x8);

      // Set new PC
      Addr HandlerBase;
      HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
      setHandlerPC(HandlerBase,tc);
      //      warn("Exception Handler At: %x \n",HandlerBase);
      //      warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));

}

void InterruptFault::invoke(ThreadContext *tc)
{
#if  FULL_SYSTEM
  DPRINTF(MipsPRA,"%s encountered.\n", name());
  //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil
  setExceptionState(tc,0x0A);
  Addr HandlerBase;


  uint8_t IV = bits(tc->readMiscRegNoEffect(MipsISA::Cause),Cause_IV);
  if (IV)// Offset 200 for release 2
      HandlerBase= 0x20 + vect() + tc->readMiscRegNoEffect(MipsISA::EBase);
  else//Ofset at 180 for release 1
      HandlerBase= vect() + tc->readMiscRegNoEffect(MipsISA::EBase);

  setHandlerPC(HandlerBase,tc);
#endif
}

#endif // FULL_SYSTEM

void ResetFault::invoke(ThreadContext *tc)
{
#if FULL_SYSTEM
  DPRINTF(MipsPRA,"%s encountered.\n", name());
  /* All reset activity must be invoked from here */
  tc->setPC(vect());
  tc->setNextPC(vect()+sizeof(MachInst));
  tc->setNextNPC(vect()+sizeof(MachInst)+sizeof(MachInst));
  DPRINTF(MipsPRA,"(%x)  -  ResetFault::invoke : PC set to %x",(unsigned)tc,(unsigned)tc->readPC());
#endif

  // Set Coprocessor 1 (Floating Point) To Usable
  tc->setMiscReg(MipsISA::Status, MipsISA::Status | 0x20000000);
}

void ReservedInstructionFault::invoke(ThreadContext *tc)
{
#if  FULL_SYSTEM
  DPRINTF(MipsPRA,"%s encountered.\n", name());
  //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil
  setExceptionState(tc,0x0A);
  Addr HandlerBase;
  HandlerBase= vect() + tc->readMiscRegNoEffect(MipsISA::EBase); // Offset 0x180 - General Exception Vector
  setHandlerPC(HandlerBase,tc);
#else
    panic("%s encountered.\n", name());
#endif
}

void ThreadFault::invoke(ThreadContext *tc)
{
  DPRINTF(MipsPRA,"%s encountered.\n", name());
  panic("%s encountered.\n", name());
}

void DspStateDisabledFault::invoke(ThreadContext *tc)
{
  DPRINTF(MipsPRA,"%s encountered.\n", name());
  panic("%s encountered.\n", name());
}

void CoprocessorUnusableFault::invoke(ThreadContext *tc)
{
#if FULL_SYSTEM
  DPRINTF(MipsPRA,"%s encountered.\n", name());
  setExceptionState(tc,0xb);
  /* The ID of the coprocessor causing the exception is stored in CoprocessorUnusableFault::coProcID */
  MiscReg cause = tc->readMiscReg(MipsISA::Cause);
  replaceBits(cause,Cause_CE_HI,Cause_CE_LO,coProcID);
  tc->setMiscRegNoEffect(MipsISA::Cause,cause);

  Addr HandlerBase;
  HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
  setHandlerPC(HandlerBase,tc);

  //      warn("Status: %x, Cause: %x\n",tc->readMiscReg(MipsISA::Status),tc->readMiscReg(MipsISA::Cause));
#else
    warn("%s (CP%d) encountered.\n", name(), coProcID);
#endif
}

} // namespace MipsISA