pra_constants.hh

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· HH 代码 · 共 503 行 · 第 1/2 页

  const unsigned Cause_TI_LO = 30;
  const unsigned Cause_CE_HI = 29;
  const unsigned Cause_CE_LO = 28;
  const unsigned Cause_DC = 27;
  const unsigned Cause_PCI = 26;
  const unsigned Cause_IV = 24;
  const unsigned Cause_WP = 23;
  const unsigned Cause_RIPL_HI = 15; // The individual bits of RIPL are also available as IP7..IP5
  const unsigned Cause_RIPL_LO = 10;
  const unsigned Cause_IP7 = 15; 
  const unsigned Cause_IP6 = 14; 
  const unsigned Cause_IP5 = 13; 
  const unsigned Cause_IP4 = 12;
  const unsigned Cause_IP3 = 11;
  const unsigned Cause_IP2 = 10;
  const unsigned Cause_IP1 = 9;
  const unsigned Cause_IP0 = 8;
  const unsigned Cause_EXCCODE_HI = 6;
  const unsigned Cause_EXCCODE_LO = 2;
  // All intermediate undefined bits must be ZERO


  // EPC Register - CP0 Reg 14, Sel 0
  // Exception Program Counter
  const unsigned EPC_HI = 31;
  const unsigned EPC_LO = 0;

  // PRId Register - CP0 Reg 15, Sel 0
  // Processor Identification register
  const unsigned PRIdCoOp_HI = 31;
  const unsigned PRIdCoOp_LO = 24;
  const unsigned PRIdCoID_HI = 23;
  const unsigned PRIdCoID_LO = 16;
  const unsigned PRIdProc_ID_HI = 15;
  const unsigned PRIdProc_ID_LO = 8;
  const unsigned PRIdRev_HI = 7;
  const unsigned PRIdRev_LO = 0;


  // EBase Register - CP0 Reg 15, Sel 1
  // Exception Base Register
  const unsigned EBase_MSB = 31; // MUST BE = 1
  const unsigned EBase_EXCEPTION_Base_HI = 29;
  const unsigned EBase_EXCEPTION_Base_LO = 12;
  const unsigned EBase_CPUNum_HI = 9;
  const unsigned EBase_CPUNum_LO = 0;
  // Undefined bits must be zero

  // Config Register - CP0 Reg 16, Sel 0
  const unsigned Config_M = 31;
  const unsigned Config_K23_HI = 30;
  const unsigned Config_K23_LO = 28;
  const unsigned Config_KU_HI = 27;
  const unsigned Config_KU_LO = 25;
  const unsigned Config_IMPL_HI = 24;
  const unsigned Config_IMPL_LO = 16;
  const unsigned Config_BE_HI = 15;
  const unsigned Config_BE_LO = 15;
  const unsigned Config_AT_HI = 14;
  const unsigned Config_AT_LO = 13;
  const unsigned Config_AR_HI = 12;
  const unsigned Config_AR_LO = 10;
  const unsigned Config_MT_HI = 9;
  const unsigned Config_MT_LO = 7;
  const unsigned Config_VI_HI = 3;
  const unsigned Config_VI_LO = 3;
  const unsigned Config_K0_HI = 2;
  const unsigned Config_K0_LO = 0;

  // Config1 Register - CP0 Reg 16, Sel 1
  const unsigned Config1_M = 31;
  const unsigned Config1_MMUSize_HI = 30;
  const unsigned Config1_MMUSize_LO = 25;
  const unsigned Config1_IS_HI = 24;
  const unsigned Config1_IS_LO = 22;
  const unsigned Config1_IL_HI = 21;
  const unsigned Config1_IL_LO = 19;
  const unsigned Config1_IA_HI = 18;
  const unsigned Config1_IA_LO = 16;
  const unsigned Config1_DS_HI = 15;
  const unsigned Config1_DS_LO = 13;
  const unsigned Config1_DL_HI = 12;
  const unsigned Config1_DL_LO = 10;
  const unsigned Config1_DA_HI = 9;
  const unsigned Config1_DA_LO = 7;
  const unsigned Config1_C2_HI = 6;
  const unsigned Config1_C2_LO = 6;
  const unsigned Config1_MD_HI = 5;
  const unsigned Config1_MD_LO = 5;
  const unsigned Config1_PC_HI = 4;
  const unsigned Config1_PC_LO = 4;
  const unsigned Config1_WR_HI = 3;
  const unsigned Config1_WR_LO = 3;
  const unsigned Config1_CA_HI = 2;
  const unsigned Config1_CA_LO = 2;
  const unsigned Config1_EP_HI = 1;
  const unsigned Config1_EP_LO = 1;
  const unsigned Config1_FP_HI = 0;
  const unsigned Config1_FP_LO = 0;


  // Config2 Register - CP0 Reg 16, Sel 2
  const unsigned Config2_M = 31;
  const unsigned Config2_TU_HI = 30;
  const unsigned Config2_TU_LO = 28;
  const unsigned Config2_TS_HI = 27;
  const unsigned Config2_TS_LO = 24;
  const unsigned Config2_TL_HI = 23;
  const unsigned Config2_TL_LO = 20;
  const unsigned Config2_TA_HI = 19;
  const unsigned Config2_TA_LO = 16;
  const unsigned Config2_SU_HI = 15;
  const unsigned Config2_SU_LO = 12;
  const unsigned Config2_SS_HI = 11;
  const unsigned Config2_SS_LO = 8;
  const unsigned Config2_SL_HI = 7;
  const unsigned Config2_SL_LO = 4;
  const unsigned Config2_SA_HI = 3;
  const unsigned Config2_SA_LO = 0;

  // Config3 Register - CP0 Reg 16, Sel 3
  const unsigned Config3_M = 31;
  const unsigned Config3_DSPP_HI = 10;
  const unsigned Config3_DSPP_LO = 10;
  const unsigned Config3_LPA_HI=7;
  const unsigned Config3_LPA_LO=7;
  const unsigned Config3_VEIC_HI=6;
  const unsigned Config3_VEIC_LO=6;
  const unsigned Config3_VINT_HI=5;
  const unsigned Config3_VINT_LO=5;
  const unsigned Config3_SP=4;
  const unsigned Config3_SP_HI=4;
  const unsigned Config3_SP_LO=4;
  const unsigned Config3_MT_HI=2;
  const unsigned Config3_MT_LO=2;
  const unsigned Config3_SM_HI=1;
  const unsigned Config3_SM_LO=1;
  const unsigned Config3_TL_HI=0;
  const unsigned Config3_TL_LO=0;


  // LLAddr Register - CP0 Reg 17, Sel 0
  // Load Linked Address (Physical)
  const unsigned LLAddr_PAddr_HI = 31;
  const unsigned LLAddr_PAddr_LO = 0;



  // WatchLo Register - CP0 Reg 18, Sel 0-n
  // See WatchHi to determine how many pairs of these registers are available
  const unsigned WatchLo_VAddr_HI = 31;
  const unsigned WatchLo_VAddr_LO = 3;
  const unsigned WatchLo_I = 2;
  const unsigned WatchLo_R = 1;
  const unsigned WatchLo_W = 0;


  // WatchHi Register - CP0 Reg 19, Sel 0-n
  const unsigned WatchHi_M = 31; // If M = 1, another pair of WatchHi/Lo registers exist
  const unsigned WatchHi_G = 30;
  const unsigned WatchHi_ASID_HI = 23;
  const unsigned WatchHi_ASID_LO = 16;
  const unsigned WatchHi_Mask_HI = 11;
  const unsigned WatchHi_Mask_LO = 3;
  const unsigned WatchHi_I = 2;
  const unsigned WatchHi_R = 1;
  const unsigned WatchHi_W = 0;

  // Debug Register - CP0 Reg 23, Sel 0

  // TraceControl Register - CP0 Reg 23, Sel 1
  // TraceControl2 Register - CP0 Reg 23, Sel 2
  // UserTraceData Register - CP0 Reg 23, Sel 3
  // TraceBPC Register - CP0 Reg 23, Sel 4
  // DEPC Register - CP0 Reg 24, Sel 0
  

  // PerfCnt Register - CP0 Reg 25, Sel 0-n
  // Each Perf. counter that exists is mapped onto even-odd select pairs of Reg 25
  // Even values are control registers, odd values are the actual counter
  // The format for the control reg is:
  const unsigned PerfCntCtl_M = 31; // Is there another pair of perf counter registers?
  const unsigned PerfCntCtl_W = 30;
  const unsigned PerfCntCtl_Event_HI = 10;
  const unsigned PerfCntCtl_Event_LO = 5;
  const unsigned PerfCntCtl_IE = 4;
  const unsigned PerfCntCtl_U = 3;
  const unsigned PerfCntCtl_S = 2;
  const unsigned PerfCntCtl_K = 1;
  const unsigned PerfCntCtl_EXL = 0;

  // The format for the counter is a 32-bit value (or 64-bit for MIPS64)
  const unsigned PerfCnt_Count_HI = 31;
  const unsigned PerfCnt_Count_LO = 0;

  // ErrCtl Register - CP0 Reg 26, Sel 0
  // This is implementation dependent, not defined by the ISA

  // CacheErr Register - CP0 Reg 27, Sel 0
  // NOTE: Page 65 of the ARM, Volume-III indicates that there are four sel. values (0-3)
  // used by the CacheErr registers. However, on page 134, only one sel value is shown
  const unsigned Cache_Err_ER = 31;
  const unsigned Cache_Err_EC = 30;
  const unsigned Cache_Err_ED = 29;
  const unsigned Cache_Err_ET = 28;
  const unsigned Cache_Err_ES = 27;
  const unsigned Cache_Err_EE = 26;
  const unsigned Cache_Err_EB = 25;
  const unsigned Cache_Err_IMPL_HI = 24;
  const unsigned Cache_Err_IMPL_LO = 22;
  const unsigned Cache_Err_Index_HI = 21;
  const unsigned Cache_Err_Index_LO = 0;

  // TagLo Register - CP0 Reg 28 - Even Selects (0,2)
  const unsigned TagLo_PTagLo_HI = 31;
  const unsigned TagLo_PTagLo_LO = 8;
  const unsigned TagLo_PState_HI = 7;
  const unsigned TagLo_PState_LO = 6;
  const unsigned TagLo_L = 5;
  const unsigned TagLo_IMPL_HI = 4;
  const unsigned TagLo_IMPL_LO = 3;
  const unsigned TagLo_P = 0;
  // undefined bits must be written 0


  // DataLo Register - CP0 Reg 28 - Odd Selects (1,3)
  const unsigned DataLo_HI = 31;
  const unsigned DataLo_LO = 0;

  // TagHi Register - CP0 Reg 29 - Even Selects (0,2)
  // Not defined by the architecture

  // DataHi Register - CP0 Reg 29 - Odd Selects (1,3)
  const unsigned DataHi_HI = 31;
  const unsigned DataHi_LO = 0;


  // ErrorEPC - CP0 Reg 30, Sel 0
  const unsigned ErrorPC_HI = 31;
  const unsigned ErrorPC_LO = 0;

  // DESAVE - CP0 Reg 31, Sel 0





} // namespace MipsISA

#endif