pra_constants.hh

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 * Authors: Jaidev Patwardhan
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#ifndef __ARCH_MIPS_PRA_CONSTANTS_HH__
#define __ARCH_MIPS_PRA_CONSTANTS_HH__

#include "arch/mips/types.hh"
//#include "config/full_system.hh"

namespace MipsISA
{
  // See MIPS32(R) Architecture Reference Manual Volume - III
  // This header file uses definitions from Revision 2.50

  // Index Status Register - CP0 Reg 0, Sel 0

  const unsigned Index_P_HI = 31;
  const unsigned Index_P_LO = 31;
  // Need to figure out how to put in the TLB specific bits here
  // For now, we assume that the entire length is used by the index field
  // In reality, Index_HI = N-1, where Ceiling(log2(TLB Entries))=N
  const unsigned Index_HI = 30;
  const unsigned Index_LO = 0;

  // CP0 Reg 0, Sel 1-3 are MT registers, see mt_constants.hh

  // Random Register - CP0 Reg 1, Sel 0
  // This has a problem similar to the Index_HI fields. We'll keep both consistent at 30 for now
  const unsigned Random_HI = 30;
  const unsigned Random_LO = 0;

  // EntryLo0 - CP0 Reg2, Sel 0  - Table 8-6, ARM Vol-3
  const unsigned EntryLo0_Fill_HI = 31; // See Table 8-8, ARM Vol III
  const unsigned EntryLo0_Fill_LO = 30;
  const unsigned EntryLo0_PFN_HI  = 29; //PFN defines the Page Frame Number (see Table 8-7, ARM Vol III)
  const unsigned EntryLo0_PFN_LO  =  6;
  const unsigned EntryLo0_C_HI    =  5; // Coherency attribute of a Page (see Table 8-8, ARM Vol III)
  const unsigned EntryLo0_C_LO    =  3;
  const unsigned EntryLo0_D_HI    =  2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception
  const unsigned EntryLo0_D_LO    =  2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception
  const unsigned EntryLo0_V_HI    =  1; // Valid Bit
  const unsigned EntryLo0_V_LO    =  1; // Valid Bit
  const unsigned EntryLo0_G_HI    =  0; // Global Bit. From the ARM Vol-III, Table 8-5:
  const unsigned EntryLo0_G_LO    =  0; // Global Bit. From the ARM Vol-III, Table 8-5:
                                        // On a TLB write, the logical AND of the G bits from EntryLo0 and EntryLo1 
                                        // becomes the G bit in the TLB entry. If the TLB entry G bit is 1, ASID comparisons are
                                        // ignored during TLB matches. On a read from a TLB entry, the G bits of both Lo0 and Lo1
                                        // reflect the state of the TLB G bit.

  // EntryLo1 - CP0 Reg3, Sel 0
  const unsigned EntryLo1_G_HI       =  0; 
  const unsigned EntryLo1_G_LO       =  0; 
  const unsigned EntryLo1_V_HI       =  1; // Valid Bit
  const unsigned EntryLo1_V_LO       =  1; // Valid Bit
  const unsigned EntryLo1_D_HI       =  2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception
  const unsigned EntryLo1_D_LO       =  2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception
  const unsigned EntryLo1_C_HI    =  5; // Coherency attribute of a Page (see Table 8-8, ARM Vol III)
  const unsigned EntryLo1_C_LO    =  3;
  const unsigned EntryLo1_PFN_HI  = 29; //PFN defines the Page Frame Number (see Table 8-7, ARM Vol III)
  const unsigned EntryLo1_PFN_LO  =  6;
  const unsigned EntryLo1_Fill_LO = 30;
  const unsigned EntryLo1_Fill_HI = 31; // See Table 8-8, ARM Vol III


  // Context Register - CP0 Reg 4, Sel 0
  const unsigned Context_PTEBase_HI = 31; // Used by the OS to point into current PTE array
  const unsigned Context_PTEBase_LO = 23; 
  const unsigned Context_BadVPN2_HI = 22; // This is written by hardware on a TLB exception. Contains bits 31-13 of the 
  const unsigned Context_BadVPN2_LO = 4;  // virtual address
  // Bits 3-0 are zeros

  // PageMask Register - CP0 Reg 5, Sel 0
  // Bits 31-29 are 0
  const unsigned PageMask_Mask_HI = 28; // (Table 8-10, ARM Vol-III) The Mask field is a bit mask in which a "1" indicates that 
  const unsigned PageMask_Mask_LO = 13; // the corresponding bit of the virtual address should not participate in the TLB match
  const unsigned PageMask_MaskX_HI = 12; // See Table 8-10, ARM Vol-III 
  const unsigned PageMask_MaskX_LO = 11;
  // Bits 10-0 are zero


  // PageGrain Register - CP0 Reg 5, Sel 1
  const unsigned PageGrain_ASE_UP_HI = 31; // ASE specific bits (SmartMIPS)
  const unsigned PageGrain_ASE_UP_LO = 30; //
  const unsigned PageGrain_ELPA = 29; // Used to enable support for large physical addresses in MIPS64 processors, unused in MIPS32
  const unsigned PageGrain_ESP = 28; // Enables support for 1KB pages (1==enabled,0==disabled), See ARM Vol-III, Table 8-12
  const unsigned PageGrain_ESP_HI = 28; // Enables support for 1KB pages (1==enabled,0==disabled), See ARM Vol-III, Table 8-12
  const unsigned PageGrain_ESP_LO = 28; // Enables support for 1KB pages (1==enabled,0==disabled), See ARM Vol-III, Table 8-12
  const unsigned PageGrain_ASE_DN_HI = 12;
  const unsigned PageGrain_ASE_DN_LO = 8;
  // Bits 27-13, 7-0 are zeros

  // Wired Register - CPO Reg 6, Sel 0
  // See note on Index register (CP0, Sel0) above
  const unsigned Wired_HI = 30;
  const unsigned Wired_LO = 0;


  // HWREna Register - CP0 Reg 7, Sel 0
  const unsigned HWREna_IMPL_HI = 31; // These bits enable access to implementation dependent hardware registers 31
  const unsigned HWREna_IMPL_LO = 30; // and 30
  const unsigned HWREna_Mask_HI = 3; // Each bit enables access to a particular hardware register. If bit 'n' is 1, HW Reg n is accessible
  const unsigned HWREna_Mask_LO = 0; // See the RDHWR instruction for more details


  // BadVAddr Register - CP0 Reg 8, Sel 0
  const unsigned BadVAddr_HI = 31;
  const unsigned BadVAddr_LO = 0;

  // Count Register - CP0 Reg 9, Sel 0
  const unsigned Count_HI = 31;
  const unsigned Count_LO = 0;

  // EntryHI Register - CP0 Reg 10, Sel 0
  const unsigned EntryHi_VPN2_HI = 31;  // This field is written by hardware on a TLB exception or on a TLB read
  const unsigned EntryHi_VPN2_LO = 13;  // and is written by software before a TLB write
  const unsigned EntryHi_VPN2X_HI = 12; // Extension to support 1KB pages
  const unsigned EntryHi_VPN2X_LO = 11;
  const unsigned EntryHi_ASID_HI = 7; // Address space identifier
  const unsigned EntryHi_ASID_LO = 0;

  // Compare Register - CP0 Reg 11, Sel 0
  const unsigned Compare_HI = 31; // Used in conjunction with Count
  const unsigned Compare_LO = 0;

  // Status Register - CP Reg 12, Sel 0
  const unsigned Status_IE_HI = 0;
  const unsigned Status_IE_LO = 0;

  const unsigned Status_EXL = 1;
  const unsigned Status_EXL_HI = 1;
  const unsigned Status_EXL_LO = 1;
  const unsigned Status_ERL_HI = 2;
  const unsigned Status_ERL_LO = 2;
  const unsigned Status_R0 = 3;
  const unsigned Status_UM = 4;
  const unsigned Status_KSU_HI = 4;  // R0 and UM are also aliased as KSU
  const unsigned Status_KSU_LO = 3;
  const unsigned Status_UX = 5;
  const unsigned Status_SX = 6;
  const unsigned Status_KX = 7;
  const unsigned Status_IM0 = 8;
  const unsigned Status_IM1 = 9;
  const unsigned Status_IM2 = 10;
  const unsigned Status_IM3 = 11;
  const unsigned Status_IM4 = 12;
  const unsigned Status_IM5 = 13;
  const unsigned Status_IM6 = 14;
  const unsigned Status_IM7 = 15;
  const unsigned Status_IPL_HI = 15;  // IM7..IM2 are also aliased as IPL
  const unsigned Status_IPL_LO = 10;
  const unsigned Status_IMPL_HI = 17;
  const unsigned Status_IMPL_LO = 16;
  const unsigned Status_NMI = 19;
  const unsigned Status_SR = 20;
  const unsigned Status_TS = 21;
  const unsigned Status_BEV = 22;
  const unsigned Status_BEV_HI = 22;
  const unsigned Status_BEV_LO = 22;
  const unsigned Status_PX = 23;
  const unsigned Status_MX = 24;
  const unsigned Status_RE = 25;
  const unsigned Status_FR = 26;
  const unsigned Status_RP = 27;
  const unsigned Status_CU3_HI = 31;
  const unsigned Status_CU3_LO = 31;
  const unsigned Status_CU2_HI = 30;
  const unsigned Status_CU2_LO = 30;
  const unsigned Status_CU1_HI = 29;
  const unsigned Status_CU1_LO = 29;
  const unsigned Status_CU0_HI = 28;
  const unsigned Status_CU0_LO = 28;

  // IntCtl Register - CP0 Reg 12, Sel 1
  // Interrupt System status and control
  const unsigned IntCtl_IPTI_HI = 31;
  const unsigned IntCtl_IPTI_LO = 29;
  const unsigned IntCtl_IPPCI_HI = 28;
  const unsigned IntCtl_IPPCI_LO = 26;
  const unsigned IntCtl_VS_HI = 9;
  const unsigned IntCtl_VS_LO = 5;
  // Bits 26-10, 4-0 are zeros

  // SRSCtl Register - CP0 Reg 12, Sel 2
  // Shadow Register Set Status and Control
  const unsigned SRSCtl_HSS_HI=29; // Highest Shadow Set
  const unsigned SRSCtl_HSS_LO=26;
  const unsigned SRSCtl_EICSS_HI=21; //EIC interrupt mode shadow set
  const unsigned SRSCtl_EICSS_LO=18;
  const unsigned SRSCtl_ESS_HI=15; // Exception Shadow Set
  const unsigned SRSCtl_ESS_LO=12;
  const unsigned SRSCtl_PSS_HI=9; // Previous Shadow Set
  const unsigned SRSCtl_PSS_LO=6;
  const unsigned SRSCtl_CSS_HI=3; // Current Shadow Set
  const unsigned SRSCtl_CSS_LO=0;

  // SRSMap Register - CP0 Reg 12, Sel 3
  // Shadow Set IPL mapping 
  const unsigned SRSMap_SSV7_HI = 31; // Shadow sets for particular vector numbers (7..0)
  const unsigned SRSMap_SSV7_LO = 28;
  const unsigned SRSMap_SSV6_HI = 27;
  const unsigned SRSMap_SSV6_LO = 24;
  const unsigned SRSMap_SSV5_HI = 23;
  const unsigned SRSMap_SSV5_LO = 20;
  const unsigned SRSMap_SSV4_HI = 19;
  const unsigned SRSMap_SSV4_LO = 16;
  const unsigned SRSMap_SSV3_HI = 15;
  const unsigned SRSMap_SSV3_LO = 12;
  const unsigned SRSMap_SSV2_HI = 11;
  const unsigned SRSMap_SSV2_LO = 8;
  const unsigned SRSMap_SSV1_HI = 7;
  const unsigned SRSMap_SSV1_LO = 4;
  const unsigned SRSMap_SSV0_HI = 3;
  const unsigned SRSMap_SSV0_LO = 20;

  // Cause Register - CP0 Reg 13, Sel 0
  const unsigned Cause_BD_HI = 31;
  const unsigned Cause_BD_LO = 31;
  const unsigned Cause_TI_HI = 30;