includes.isa

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· ISA 代码 · 共 101 行

// -*- mode:c++ -*-

// Copyright (c) 2007 MIPS Technologies, Inc.  All Rights Reserved

//  This software is part of the M5 simulator.

//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
//  TO THESE TERMS AND CONDITIONS.

//  Permission is granted to use, copy, create derivative works and
//  distribute this software and such derivative works for any purpose,
//  so long as (1) the copyright notice above, this grant of permission,
//  and the disclaimer below appear in all copies and derivative works
//  made, (2) the copyright notice above is augmented as appropriate to
//  reflect the addition of any new copyrightable work in a derivative
//  work (e.g., Copyright (c) <Publication Year> Copyright Owner), and (3)
//  the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
//  advertising or publicity pertaining to the use or distribution of
//  this software without specific, written prior authorization.

//  THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.

//Authors: Korey L. Sewell

////////////////////////////////////////////////////////////////////
//
// Output include file directives.
//

output header {{
#include <sstream>
#include <iostream>
#include <iomanip>

#include "arch/mips/isa_traits.hh"
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
}};

output decoder {{
#include "arch/mips/isa_traits.hh"
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"  
#include "arch/mips/faults.hh"
#include "arch/mips/isa_traits.hh"
#include "arch/mips/pra_constants.hh"
#include "arch/mips/dt_constants.hh"
#include "arch/mips/mt_constants.hh"
#include "arch/mips/utility.hh"
#include "arch/mips/dsp.hh"
#include "mem/packet.hh"

#include <math.h>
#if defined(linux)
#include <fenv.h>
#endif

using namespace MipsISA;
}};

output exec {{
#include "arch/mips/faults.hh"
#include "arch/mips/isa_traits.hh"
#include "arch/mips/utility.hh"
#include "arch/mips/dsp.hh"
#include "arch/mips/pra_constants.hh"
#include "arch/mips/dt_constants.hh"
#include "arch/mips/mt_constants.hh"

#include <math.h>
#if defined(linux)
#include <fenv.h>
#endif

#include "cpu/base.hh"
#include "cpu/exetrace.hh"

#include "mem/packet.hh"
#include "mem/packet_access.hh"

#include "sim/sim_exit.hh"
#include "sim/eventq.hh"
#include "sim/sim_events.hh"

using namespace MipsISA;
}};