mem.isa

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· ISA 代码 · 共 882 行 · 第 1/2 页

	Fault fault = NoFault;

	%(fp_enable_check)s;
	%(op_decl)s;
	%(op_rd)s;

	EA = xc->getEA();
	
	if (fault == NoFault) {
	    %(memacc_code)s;
	}

	if (fault == NoFault) {
	    fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
			      memAccessFlags, NULL);
	    // @NOTE: Need to Call Complete Access to Set Trace Data
	    //if (traceData) { traceData->setData(Mem); }
	}

	return fault;
    }
}};

def template StoreCondMemAccExecute {{
    Fault
    %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
				   Trace::InstRecord *traceData) const
    {
	Addr EA;
	Fault fault = NoFault;
	uint64_t write_result = 0;

	%(fp_enable_check)s;
	%(op_decl)s;
	%(op_rd)s;
	EA = xc->getEA();
	
	if (fault == NoFault) {
	    %(memacc_code)s;
	}

	if (fault == NoFault) {
	    fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
			      memAccessFlags, &write_result);
	    if (traceData) { traceData->setData(Mem); }
	}

	if (fault == NoFault) {
	    %(postacc_code)s;
	}

	if (fault == NoFault) {
	    %(op_wb)s;
	}

	return fault;
    }
}};

def template StoreExecute {{
    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
				  Trace::InstRecord *traceData) const
    {
	Addr EA;
	Fault fault = NoFault;

	%(fp_enable_check)s;
	%(op_decl)s;
	%(op_rd)s;
	%(ea_code)s;

	if (fault == NoFault) {
	    %(memacc_code)s;
	}

	if (fault == NoFault) {
	    fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
			      memAccessFlags, NULL);
	    if (traceData) { traceData->setData(Mem); }
	}

	if (fault == NoFault) {
	    %(postacc_code)s;
	}

	if (fault == NoFault) {
	    %(op_wb)s;
	}

	return fault;
    }
}};


def template StoreFPExecute {{
    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
				  Trace::InstRecord *traceData) const
    {
	Addr EA;
	Fault fault = NoFault;

	%(fp_enable_check)s;
	if(fault != NoFault)
	  return fault;
	%(op_decl)s;
	%(op_rd)s;
	%(ea_code)s;

	if (fault == NoFault) {
	    %(memacc_code)s;
	}

	if (fault == NoFault) {
	    fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
			      memAccessFlags, NULL);
	    if (traceData) { traceData->setData(Mem); }
	}

	if (fault == NoFault) {
	    %(postacc_code)s;
	}

	if (fault == NoFault) {
	    %(op_wb)s;
	}

	return fault;
    }
}};

def template StoreCondExecute {{
    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
				  Trace::InstRecord *traceData) const
    {
	Addr EA;
	Fault fault = NoFault;
	uint64_t write_result = 0;

	%(fp_enable_check)s;
	%(op_decl)s;
	%(op_rd)s;
	%(ea_code)s;

	if (fault == NoFault) {
	    %(memacc_code)s;
	}

	if (fault == NoFault) {
	    fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
			      memAccessFlags, &write_result);
	    if (traceData) { traceData->setData(Mem); }
	}

	if (fault == NoFault) {
	    %(postacc_code)s;
	}

	if (fault == NoFault) {
	    %(op_wb)s;
	}

	return fault;
    }
}};

def template StoreInitiateAcc {{
    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
                                      Trace::InstRecord *traceData) const
    {
	Addr EA;
	Fault fault = NoFault;

	%(fp_enable_check)s;
	%(op_decl)s;
	%(op_rd)s;
	%(ea_code)s;

	if (fault == NoFault) {
	    %(memacc_code)s;
	}

	if (fault == NoFault) {
	    fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
			      memAccessFlags, NULL);
	    if (traceData) { traceData->setData(Mem); }
	}

        return fault;
    }
}};


def template StoreCompleteAcc {{
    Fault %(class_name)s::completeAcc(Packet *pkt,
                                      %(CPU_exec_context)s *xc,
                                      Trace::InstRecord *traceData) const
    {
	Fault fault = NoFault;

	%(fp_enable_check)s;
        %(op_dest_decl)s;

	if (fault == NoFault) {
	    %(postacc_code)s;
	}

	if (fault == NoFault) {
	    %(op_wb)s;

	    if (traceData) { traceData->setData(getMemData(xc, pkt)); }
	}

	return fault;
    }
}};


def template StoreCompleteAcc {{
    Fault %(class_name)s::completeAcc(Packet *pkt,
                                      %(CPU_exec_context)s *xc,
                                      Trace::InstRecord *traceData) const
    {
	Fault fault = NoFault;

        %(op_dest_decl)s;

	if (fault == NoFault) {
	    %(postacc_code)s;
	}

	if (fault == NoFault) {
	    %(op_wb)s;

	    if (traceData) { traceData->setData(getMemData(xc, pkt)); }
	}

	return fault;
    }
}}; 

def template StoreCondCompleteAcc {{
    Fault %(class_name)s::completeAcc(Packet *pkt,
                                      %(CPU_exec_context)s *xc,
                                      Trace::InstRecord *traceData) const
    {
	Fault fault = NoFault;

	%(fp_enable_check)s;
        %(op_dest_decl)s;

	uint64_t write_result = pkt->req->getExtraData();

	if (fault == NoFault) {
	    %(postacc_code)s;
	}

	if (fault == NoFault) {
	    %(op_wb)s;
	}

	return fault;
    }
}};


def template MiscMemAccExecute {{
    Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
					  Trace::InstRecord *traceData) const
    {
	Addr EA;
	Fault fault = NoFault;

	%(fp_enable_check)s;
	%(op_decl)s;
	%(op_rd)s;
	EA = xc->getEA();

	if (fault == NoFault) {
	    %(memacc_code)s;
	}

	return NoFault;
    }
}};

def template MiscExecute {{
    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
				  Trace::InstRecord *traceData) const
    {
	Addr EA;
	Fault fault = NoFault;

	%(fp_enable_check)s;
	%(op_decl)s;
	%(op_rd)s;
	%(ea_code)s;

	if (fault == NoFault) {
	    %(memacc_code)s;
	}

	return NoFault;
    }
}};

def template MiscInitiateAcc {{
    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
                                      Trace::InstRecord *traceData) const
    {
        panic("Misc instruction does not support split access method!");
	return NoFault;
    }
}};


def template MiscCompleteAcc {{
    Fault %(class_name)s::completeAcc(Packet *pkt,
                                      %(CPU_exec_context)s *xc,
                                      Trace::InstRecord *traceData) const
    {
        panic("Misc instruction does not support split access method!");

        return NoFault;
    }
}};


def template MiscMemAccSize {{
    int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc) 
    {
        panic("Misc instruction does not support split access method!");
        return 0;
    }
}};

def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
		     mem_flags = [], inst_flags = []) {{
    (header_output, decoder_output, decode_block, exec_output) = \
        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                      decode_template = ImmNopCheckDecode,
                      exec_template_base = 'Load')
}};


def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
		     mem_flags = [], inst_flags = []) {{
    (header_output, decoder_output, decode_block, exec_output) = \
        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                      exec_template_base = 'Store')
}};
 
def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
		     mem_flags = [], inst_flags = []) {{
    inst_flags += ['IsIndexed']
    (header_output, decoder_output, decode_block, exec_output) = \
        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                      decode_template = ImmNopCheckDecode,
                      exec_template_base = 'Load')
}};

def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
                     mem_flags = [], inst_flags = []) {{
    inst_flags += ['IsIndexed']
    (header_output, decoder_output, decode_block, exec_output) = \
        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                      exec_template_base = 'Store')
}};

def format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
                     mem_flags = [], inst_flags = []) {{
    inst_flags += ['IsIndexed', 'IsFloating']
    (header_output, decoder_output, decode_block, exec_output) = \
        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                      decode_template = ImmNopCheckDecode,
                      exec_template_base = 'Load')
}};

def format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
                     mem_flags = [], inst_flags = []) {{
    inst_flags += ['IsIndexed', 'IsFloating']
    (header_output, decoder_output, decode_block, exec_output) = \
        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                      exec_template_base = 'Store')
}};


def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
		     mem_flags = [], inst_flags = []) {{
    decl_code = 'uint32_t mem_word = Mem.uw;\n'
    decl_code += 'uint32_t unalign_addr = Rs + disp;\n'
    decl_code += 'uint32_t byte_offset = unalign_addr & 3;\n'
    decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'			
    decl_code += '\tbyte_offset ^= 3;\n'			
    decl_code += '#endif\n'			

    memacc_code = decl_code + memacc_code      

    (header_output, decoder_output, decode_block, exec_output) = \
        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                      decode_template = ImmNopCheckDecode,
                      exec_template_base = 'Load')
}};

def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
		     mem_flags = [], inst_flags = []) {{
    decl_code = 'uint32_t mem_word = 0;\n'
    decl_code += 'uint32_t unaligned_addr = Rs + disp;\n'
    decl_code += 'uint32_t byte_offset = unaligned_addr & 3;\n'
    decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'			
    decl_code += '\tbyte_offset ^= 3;\n'			
    decl_code += '#endif\n'			
    decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n'
    #decl_code += 'xc->readFunctional(EA,(uint32_t&)mem_word);'
    memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' 

    (header_output, decoder_output, decode_block, exec_output) = \
        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                      exec_template_base = 'Store')
}};

def format Prefetch(ea_code = {{ EA = Rs + disp; }},
			  mem_flags = [], pf_flags = [], inst_flags = []) {{
    pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
    pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
                                  'IsDataPrefetch', 'MemReadOp']

    (header_output, decoder_output, decode_block, exec_output) = \
	LoadStoreBase(name, Name, ea_code,
		      'xc->prefetch(EA, memAccessFlags);',
		      pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')

}};

def format StoreCond(memacc_code, postacc_code,
		     ea_code = {{ EA = Rs + disp; }},
		     mem_flags = [], inst_flags = []) {{
    (header_output, decoder_output, decode_block, exec_output) = \
        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
		      postacc_code, exec_template_base = 'StoreCond')
}};