mem.isa

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· ISA 代码 · 共 882 行 · 第 1/2 页

// -*- mode:c++ -*-

// Copyright (c) 2007 MIPS Technologies, Inc.  All Rights Reserved

//  This software is part of the M5 simulator.

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//Authors: Steve Reinhardt
//         Korey L. Sewell

////////////////////////////////////////////////////////////////////
//
// Memory-format instructions
//

output header {{
    /**
     * Base class for general Mips memory-format instructions.
     */
    class Memory : public MipsStaticInst
    {
      protected:

	/// Memory request flags.  See mem_req_base.hh.
        unsigned memAccessFlags;
	/// Pointer to EAComp object.
	const StaticInstPtr eaCompPtr;
	/// Pointer to MemAcc object.
	const StaticInstPtr memAccPtr;

	/// Displacement for EA calculation (signed).
	int32_t disp;

	/// Constructor
	Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
	       StaticInstPtr _eaCompPtr = nullStaticInstPtr,
	       StaticInstPtr _memAccPtr = nullStaticInstPtr)
	    : MipsStaticInst(mnem, _machInst, __opClass),
	      memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr),
      	      disp(sext<16>(OFFSET))
	{
	}

	std::string
	generateDisassembly(Addr pc, const SymbolTable *symtab) const;

      public:

	const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
	const StaticInstPtr &memAccInst() const { return memAccPtr; }

	unsigned memAccFlags() { return memAccessFlags; }
    };

     /**
     * Base class for a few miscellaneous memory-format insts
     * that don't interpret the disp field
     */
    class MemoryNoDisp : public Memory
    {
      protected:
	/// Constructor
	MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
		     StaticInstPtr _eaCompPtr = nullStaticInstPtr,
		     StaticInstPtr _memAccPtr = nullStaticInstPtr)
	    : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
	{
	}

	std::string
	generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };
}};


output decoder {{
    std::string
    Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
	return csprintf("%-10s %c%d, %d(r%d)", mnemonic,
			flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
    }

    std::string
    MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
	return csprintf("%-10s %c%d, r%d(r%d)", mnemonic,
			flags[IsFloating] ? 'f' : 'r', 
			flags[IsFloating] ? FD : RD, 
			RS, RT);
    }

}};

output exec {{
    /** return data in cases where there the size of data is only
        known in the packet
    */
    uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet) {
	switch (packet->getSize()) 
	{
	  case 1:
	    return packet->get<uint8_t>();

	  case 2:
	    return packet->get<uint16_t>();

	  case 4:
	    return packet->get<uint32_t>();

	  case 8:
	    return packet->get<uint64_t>();

	  default:
	    std::cerr << "bad store data size = " << packet->getSize() << std::endl;

	    assert(0);
	    return 0;
	} 
    }    
    

}};

def template LoadStoreDeclare {{
    /**
     * Static instruction class for "%(mnemonic)s".
     */
    class %(class_name)s : public %(base_class)s
    {
      protected:

	/**
	 * "Fake" effective address computation class for "%(mnemonic)s".
	 */
	class EAComp : public %(base_class)s
	{
	  public:
	    /// Constructor
	    EAComp(ExtMachInst machInst);

            %(BasicExecDeclare)s
	};

	/**
	 * "Fake" memory access instruction class for "%(mnemonic)s".
	 */
	class MemAcc : public %(base_class)s
	{
	  public:
	    /// Constructor
	    MemAcc(ExtMachInst machInst);

            %(BasicExecDeclare)s
	};

      public:

	/// Constructor.
	%(class_name)s(ExtMachInst machInst);

	%(BasicExecDeclare)s

        %(InitiateAccDeclare)s

        %(CompleteAccDeclare)s

	%(MemAccSizeDeclare)s
    };
}};


def template InitiateAccDeclare {{
    Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};


def template CompleteAccDeclare {{
    Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
}};

def template MemAccSizeDeclare {{
    int memAccSize(%(CPU_exec_context)s *xc);
}};


def template MiscMemAccSize {{
    int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc) 
    {
        panic("Misc instruction does not support split access method!");
        return 0;
    }
}};

def template EACompConstructor {{
    /** TODO: change op_class to AddrGenOp or something (requires
     * creating new member of OpClass enum in op_class.hh, updating
     * config files, etc.). */
    inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst)
	: %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
    {
	%(constructor)s;
    }
}};


def template MemAccConstructor {{
    inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst)
	: %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
    {
	%(constructor)s;
    }
}};


def template LoadStoreConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
	 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
			  new EAComp(machInst), new MemAcc(machInst))
    {
	%(constructor)s;
    }
}};


def template EACompExecute {{
    Fault
    %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
				   Trace::InstRecord *traceData) const
    {
	Addr EA;
	Fault fault = NoFault;

        if (this->isFloating()) {
            %(fp_enable_check)s;

            if(fault != NoFault)
                return fault;
        }

	%(op_decl)s;
	%(op_rd)s;
	%(ea_code)s;

	// NOTE: Trace Data is written using execute or completeAcc templates
	if (fault == NoFault) {
	    xc->setEA(EA);
	}

	return fault;
    }
}};

def template LoadStoreFPEACompExecute {{
    Fault
    %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
				   Trace::InstRecord *traceData) const
    {
	Addr EA;
	Fault fault = NoFault;

	%(fp_enable_check)s;
	if(fault != NoFault)
	  return fault;
	%(op_decl)s;
	%(op_rd)s;
	%(ea_code)s;

	// NOTE: Trace Data is written using execute or completeAcc templates
	if (fault == NoFault) {
	    xc->setEA(EA);
	}

	return fault;
    }
}};


def template LoadMemAccExecute {{
    Fault
    %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
				   Trace::InstRecord *traceData) const
    {
	Addr EA;

        Fault fault = NoFault;

        if (this->isFloating()) {
            %(fp_enable_check)s;

            if(fault != NoFault)
                return fault;
        }

	%(op_decl)s;
	%(op_rd)s;

	EA = xc->getEA();

	fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);

	%(memacc_code)s;

	// NOTE: Write back data using execute or completeAcc templates

	return fault;
    }
}};


def template LoadExecute {{
    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
				  Trace::InstRecord *traceData) const
    {
	Addr EA;
	Fault fault = NoFault;

        if (this->isFloating()) {
            %(fp_enable_check)s;

            if(fault != NoFault)
                return fault;
        }

	%(op_decl)s;
	%(op_rd)s;
	%(ea_code)s;

	if (fault == NoFault) {
	    fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
	    %(memacc_code)s;
	}

	if (fault == NoFault) {
	    %(op_wb)s;
	}

	return fault;
    }
}};


def template LoadInitiateAcc {{
    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
                                      Trace::InstRecord *traceData) const
    {
	Addr EA;
	Fault fault = NoFault;

        if (this->isFloating()) {
            %(fp_enable_check)s;

            if(fault != NoFault)
                return fault;
        }

	%(op_src_decl)s;
	%(op_rd)s;
	%(ea_code)s;

	if (fault == NoFault) {
	    fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
	}

        return fault;
    }
}};

def template LoadCompleteAcc {{
    Fault %(class_name)s::completeAcc(Packet *pkt,
                                      %(CPU_exec_context)s *xc,
                                      Trace::InstRecord *traceData) const
    {
	Fault fault = NoFault;

        if (this->isFloating()) {
            %(fp_enable_check)s;

            if(fault != NoFault)
                return fault;
        }

	%(op_decl)s;
	%(op_rd)s;

	Mem = pkt->get<typeof(Mem)>();

	if (fault == NoFault) {
	    %(memacc_code)s;
	}

	if (fault == NoFault) {
	    %(op_wb)s;
	}

	return fault;
    }
}};


def template LoadStoreMemAccSize {{
    int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc) 
    {
	// Return the memory access size in bytes
	return (%(mem_acc_size)d / 8); 
    }
}};

def template StoreMemAccExecute {{
    Fault
    %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
				   Trace::InstRecord *traceData) const
    {
	Addr EA;