base.isa
来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· ISA 代码 · 共 118 行
ISA
118 行
// -*- mode:c++ -*-// Copyright (c) 2007 MIPS Technologies, Inc. All Rights Reserved// This software is part of the M5 simulator.// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING// TO THESE TERMS AND CONDITIONS.// Permission is granted to use, copy, create derivative works and// distribute this software and such derivative works for any purpose,// so long as (1) the copyright notice above, this grant of permission,// and the disclaimer below appear in all copies and derivative works// made, (2) the copyright notice above is augmented as appropriate to// reflect the addition of any new copyrightable work in a derivative// work (e.g., Copyright (c) <Publication Year> Copyright Owner), and (3)// the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any// advertising or publicity pertaining to the use or distribution of// this software without specific, written prior authorization.// THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.//Authors: Korey L. Sewell//////////////////////////////////////////////////////////////////////// Base class for MIPS instructions, and some support functions////Outputs to decoder.hhoutput header {{ using namespace MipsISA; /** * Base class for all MIPS static instructions. */ class MipsStaticInst : public StaticInst { protected: // Constructor MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass) : StaticInst(mnem, _machInst, __opClass) { } /// Print a register name for disassembly given the unique /// dependence tag number (FP or int). void printReg(std::ostream &os, int reg) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; };}};//Ouputs to decoder.ccoutput decoder {{ void MipsStaticInst::printReg(std::ostream &os, int reg) const { if (reg < FP_Base_DepTag) { ccprintf(os, "r%d", reg); } else { ccprintf(os, "f%d", reg - FP_Base_DepTag); } } std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; ccprintf(ss, "%-10s ", mnemonic); // Need to find standard way to not print // this info. Maybe add bool variable to // class? if (strcmp(mnemonic, "syscall") != 0) { if(_numDestRegs > 0){ printReg(ss, _destRegIdx[0]); } if(_numSrcRegs > 0) { ss << ", "; printReg(ss, _srcRegIdx[0]); } if(_numSrcRegs > 1) { ss << ", "; printReg(ss, _srcRegIdx[1]); } } // Should we define a separate inst. class // just for two insts? if (strcmp(mnemonic, "sll") == 0 || strcmp(mnemonic, "sra") == 0) { ccprintf(ss,", %d",SA); } return ss.str(); }}};
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