decoder.isa

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· ISA 代码 · 共 1,286 行 · 第 1/5 页

                                NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
                                /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */
                                /* Addr Shift Amount for 1KB or larger pages */
                                //	    warn("PTE->Mask: %x\n",pte->Mask);
                                if((NewEntry.Mask & 0xFFFF) == 3){
                                  NewEntry.AddrShiftAmount = 12;
                                } else if((NewEntry.Mask & 0xFFFF) == 0x0000){
                                  NewEntry.AddrShiftAmount = 10;
                                } else if((NewEntry.Mask & 0xFFFC) == 0x000C){
                                  NewEntry.AddrShiftAmount = 14;
                                } else if((NewEntry.Mask & 0xFFF0) == 0x0030){
                                  NewEntry.AddrShiftAmount = 16;
                                } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){
                                  NewEntry.AddrShiftAmount = 18;
                                } else if((NewEntry.Mask & 0xFF00) == 0x0300){
                                  NewEntry.AddrShiftAmount = 20;
                                } else if((NewEntry.Mask & 0xFC00) == 0x0C00){
                                  NewEntry.AddrShiftAmount = 22;
                                } else if((NewEntry.Mask & 0xF000) == 0x3000){
                                  NewEntry.AddrShiftAmount = 24;
                                } else if((NewEntry.Mask & 0xC000) == 0xC000){
                                  NewEntry.AddrShiftAmount = 26;
                                } else if((NewEntry.Mask & 0x30000) == 0x30000){
                                  NewEntry.AddrShiftAmount = 28;
                                } else {
                                  fatal("Invalid Mask Pattern Detected!\n");
                                }
                                NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1);

                                MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr();
                                MiscReg c3=xc->readMiscReg(MipsISA::Config3);
                                MiscReg pg=xc->readMiscReg(MipsISA::PageGrain);
                                int SP=0;
                                if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){
                                  SP=1;
                                }
                                Ptr->insertAt(NewEntry,Random,SP);
                }});

                0x08: tlbp({{
                               int TLB_Index;
                               Addr VPN;
                               if(PageGrain_ESP == 1 && Config3_SP ==1){
                                 VPN = EntryHi >> 11;
                               } else {
                                 VPN = ((EntryHi >> 11) & 0xFFFFFFFC); // Mask off lower 2 bits
                               }
                               TLB_Index = xc->tcBase()->getITBPtr()->probeEntry(VPN,EntryHi_ASID);
                               if(TLB_Index != -1){  // Check TLB for entry matching EntryHi
                                 Index=TLB_Index;
                                 //			    warn("\ntlbp: Match Found!\n");
                               } else {// else, set Index = 1<<31
                                 Index = (1<<31);
                               }
                        }});
              }
              format CP0Unimpl {
                0x20: wait();
              }
               default: CP0Unimpl::unknown();

            }
        }

        //Table A-13 MIPS32 COP1 Encoding of rs Field
        0x1: decode RS_MSB {

            0x0: decode RS_HI {
                0x0: decode RS_LO {
                    format CP1Control {
                        0x0: mfc1 ({{ Rt.uw = Fs.uw; }});

                        0x2: cfc1({{
                            switch (FS)
                            {
                              case 0:
                                Rt = FIR;
                                break;
                              case 25:
                                Rt = 0 | (FCSR & 0xFE000000) >> 24 | (FCSR & 0x00800000) >> 23;
                                break;
                              case 26:
                                Rt = 0 | (FCSR & 0x0003F07C);
                                break;
                              case 28:
                                Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003);
                                break;
                              case 31:
                                Rt = FCSR;
                                break;
                              default:
                                warn("FP Control Value (%d) Not Valid");
                            }
                            //			    warn("FCSR: %x, FS: %d, FIR: %x, Rt: %x\n",FCSR, FS, FIR, Rt);
                        }});

                        0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}});

                        0x4: mtc1 ({{ Fs.uw = Rt.uw;       }});

                        0x6: ctc1({{
                            switch (FS)
                            {
                              case 25:
                                FCSR = 0 | (Rt.uw<7:1> << 25) // move 31...25
                                    | (FCSR & 0x01000000) // bit 24
                                    | (FCSR & 0x004FFFFF);// bit 22...0
                                break;

                              case 26:
                                FCSR = 0 | (FCSR & 0xFFFC0000) // move 31...18
                                    | Rt.uw<17:12> << 12           // bit 17...12
                                    | (FCSR & 0x00000F80) << 7// bit 11...7
                                    | Rt.uw<6:2> << 2              // bit 6...2
                                    | (FCSR & 0x00000002);     // bit 1...0
                                break;

                              case 28:
                                FCSR = 0 | (FCSR & 0xFE000000) // move 31...25
                                    | Rt.uw<2:2> << 24       // bit 24
                                    | (FCSR & 0x00FFF000) << 23// bit 23...12
                                    | Rt.uw<11:7> << 7       // bit 24
                                    | (FCSR & 0x000007E)
                                    | Rt.uw<1:0>;// bit 22...0
                                break;

                              case 31:
                                FCSR  = Rt.uw;
                                break;

                              default:
                                panic("FP Control Value (%d) Not Available. Ignoring Access to"
                                      "Floating Control Status Register", FS);
                            }
                        }});

                        0x7: mthc1({{
                             uint64_t fs_hi = Rt.uw;
                             uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF;
                             Fs.ud = (fs_hi << 32) | fs_lo;
                        }});

                    }
                    format CP1Unimpl {
                      0x1: dmfc1();
                      0x5: dmtc1();
                    }
                   }

                0x1:
                   decode RS_LO {
                     0x0:
                     decode ND {
                       format Branch {
                         0x0: decode TF {
                           0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
                                       }});
                           0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
                                       }});
                         }
                         0x1: decode TF {
                           0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
                                        }}, Likely);
                           0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
                                        }}, Likely);
                         }
                       }
                     }
                   format CP1Unimpl {
                     0x1: bc1any2();
                     0x2: bc1any4();
                     default: unknown();
                   }
                   }
            }

            0x1: decode RS_HI {
                0x2: decode RS_LO {
                    //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
                    //(( single-precision floating point))
                    0x0: decode FUNCTION_HI {
                        0x0: decode FUNCTION_LO {
                            format FloatOp {
                                0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}});
                                0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}});
                                0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}});
                                0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}});
                                0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}});
                                0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}});
                                0x7: neg_s({{ Fd.sf = -Fs.sf;}});
                            }

                            0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf;}});
                        }

                        0x1: decode FUNCTION_LO {
                            format FloatConvertOp {
                                0x0: round_l_s({{ val = Fs.sf; }}, ToLong,
                                               Round);
                                0x1: trunc_l_s({{ val = Fs.sf; }}, ToLong,
                                               Trunc);
                                0x2: ceil_l_s({{ val = Fs.sf; }}, ToLong,
                                               Ceil);
                                0x3: floor_l_s({{ val = Fs.sf; }}, ToLong,
                                               Floor);
                                0x4: round_w_s({{ val = Fs.sf; }}, ToWord,
                                               Round);
                                0x5: trunc_w_s({{ val = Fs.sf; }}, ToWord,
                                               Trunc);
                                0x6: ceil_w_s({{ val = Fs.sf; }}, ToWord,
                                               Ceil);
                                0x7: floor_w_s({{ val = Fs.sf; }}, ToWord,
                                               Floor);
                            }
                        }

                        0x2: decode FUNCTION_LO {
                            0x1: decode MOVCF {
                                format BasicOp {
                                    0x0: movf_s({{ Fd = (getCondCode(FCSR,CC) == 0) ? Fs : Fd; }});
                                    0x1: movt_s({{ Fd = (getCondCode(FCSR,CC) == 1) ? Fs : Fd; }});
                                }
                            }

                            format BasicOp {
                                0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }});
                                0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }});
                            }

                            format FloatOp {
                                0x5: recip_s({{ Fd = 1 / Fs; }});
                                0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}});
                            }
                            format CP1Unimpl {
                              default: unknown();
                            }
                        }
                        0x3: CP1Unimpl::unknown();

                        0x4: decode FUNCTION_LO {
                            format FloatConvertOp {
                                0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble);
                                0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord);
                                0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong);
                            }

                            0x6: FloatOp::cvt_ps_s({{
                                    Fd.ud = (uint64_t) Fs.uw << 32 |
                                            (uint64_t) Ft.uw;
                                }});
                            format CP1Unimpl {
                              default: unknown();
                            }
                        }
                        0x5: CP1Unimpl::unknown();

                        0x6: decode FUNCTION_LO {
                            format FloatCompareOp {