decoder.isa

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· ISA 代码 · 共 1,286 行 · 第 1/5 页

                                              data = 0 | (FCSR & 0xFE000000) // move 31...25
                                                  | Rt.uw<2:2> << 24       // bit 24
                                                  | (FCSR & 0x00FFF000) << 23// bit 23...12
                                                  | Rt.uw<11:7> << 7       // bit 24
                                                  | (FCSR & 0x000007E)
                                                  | Rt.uw<1:0>;// bit 22...0
                                              break;

                                            case 31:
                                              data  = Rt.uw;
                                              break;

                                            default:
                                              panic("FP Control Value (%d) Not Available. Ignoring Access to"
                                                    "Floating Control Status Register", FS);
                                          }
                                          xc->setRegOtherThread(FCSR, data);
                                       }});
                               default: CP0Unimpl::unknown();
                        }
                    }
                }


                0xB: decode RD {
                    format MT_Control {
                        0x0: decode POS {
                            0x0: decode SEL {
                                0x1: decode SC {
                                    0x0: dvpe({{ Rt = MVPControl;
                                                 if (VPEConf0<VPEC0_MVP:> == 1) {
                                                     MVPControl = insertBits(MVPControl, MVPC_EVP, 0);
                                                 }
                                              }});
                                    0x1: evpe({{ Rt = MVPControl;
                                                 if (VPEConf0<VPEC0_MVP:> == 1) {
                                                     MVPControl = insertBits(MVPControl, MVPC_EVP, 1);
                                                 }
                                              }});
                                   default:CP0Unimpl::unknown();
                                }
                               default:CP0Unimpl::unknown();
                            }
                        default:CP0Unimpl::unknown();
                      }

                        0x1: decode POS {
                            0xF: decode SEL {
                                0x1: decode SC {
                                    0x0: dmt({{ Rt = VPEControl;
                                                VPEControl = insertBits(VPEControl, VPEC_TE, 0);
                                         }});
                                    0x1: emt({{ Rt = VPEControl;
                                                VPEControl = insertBits(VPEControl, VPEC_TE, 1);
                                         }});
                                   default:CP0Unimpl::unknown();
                                }
                               default:CP0Unimpl::unknown();
                            }
                            default:CP0Unimpl::unknown();
                        }
                    }
                    0xC: decode POS {
                      0x0: decode SC {
                        0x0: CP0Control::di({{
                            if(Config_AR >= 1) // Rev 2.0 or beyond?
                                {
                                  Rt = Status;
                                  Status_IE = 0;
                                }
                            else // Enable this else branch once we actually set values for Config on init
                              {
                                fault = new ReservedInstructionFault();
                              }
                          }});
                        0x1: CP0Control::ei({{
                            if(Config_AR >= 1)
                              {
                                Rt = Status;
                                Status_IE = 1;
                              }
                            else
                              {
                                fault = new ReservedInstructionFault();
                              }
                          }});
                        default:CP0Unimpl::unknown();
                      }
                    }
                default: CP0Unimpl::unknown();
                }
                format CP0Control {
                    0xA: rdpgpr({{
                      if(Config_AR >= 1)
                        { // Rev 2 of the architecture
                          Rd = xc->tcBase()->readIntReg(RT + NumIntRegs * SRSCtl_PSS);
                        }
                      else
                        {
                          fault = new ReservedInstructionFault();
                        }
                         }});
                    0xE: wrpgpr({{
                      if(Config_AR >= 1)
                        { // Rev 2 of the architecture
                          xc->tcBase()->setIntReg(RD + NumIntRegs * SRSCtl_PSS,Rt);
                          //			  warn("Writing %d to %d, PSS: %d, SRS: %x\n",Rt,RD + NumIntRegs * SRSCtl_PSS, SRSCtl_PSS,SRSCtl);
                        }
                      else
                        {
                          fault = new ReservedInstructionFault();
                        }

                         }});
                }

               }

            //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
            0x1: decode FUNCTION {
              format CP0Control {
                0x18: eret({{
                               DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC);
                               // Ugly hack to get the value of Status_EXL
                               if(Status_EXL == 1){
                                 DPRINTF(MipsPRA,"ERET EXL Hack\n");
                               }
                  if(Status_ERL == 1){
                    Status_ERL = 0;
                    NPC = ErrorEPC;
                    NNPC = ErrorEPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break
                  }
                  else {
                    NPC = EPC;
                    NNPC = EPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break
                    Status_EXL = 0;
                    if(Config_AR >=1 && SRSCtl_HSS > 0 && Status_BEV == 0){
                      SRSCtl_CSS = SRSCtl_PSS;
                      //xc->setShadowSet(SRSCtl_PSS);
                    }
                  }
                  LLFlag = 0;
                 }},IsReturn,IsSerializing,IsERET);

                0x1F: deret({{
                  // if(EJTagImplemented()) {
                  if(Debug_DM == 1){
                    Debug_DM = 1;
                    Debug_IEXI = 0;
                    NPC = DEPC;
                  }
                  else
                    {
                      // Undefined;
                    }
                  //} // EJTag Implemented
                  //else {
                  // Reserved Instruction Exception
                  //}
                 }},IsReturn,IsSerializing,IsERET);
              }
              format CP0TLB {
                0x01: tlbr({{
                    MipsISA::PTE *PTEntry = xc->tcBase()->getITBPtr()->getEntry(Index & 0x7FFFFFFF);
                    if(PTEntry == NULL)
                      {
                        fatal("Invalid PTE Entry received on a TLBR instruction\n");
                      }
                    /* Setup PageMask */
                    PageMask = (PTEntry->Mask << 11); // If 1KB pages are not enabled, a read of PageMask must return 0b00 in bits 12, 11
                    /* Setup EntryHi */
                    EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid));
                    /* Setup Entry Lo0 */
                    EntryLo0 = ((PTEntry->PFN0 << 6) | (PTEntry->C0 << 3) | (PTEntry->D0 << 2) | (PTEntry->V0 << 1) | PTEntry->G);
                    /* Setup Entry Lo1 */
                    EntryLo1 = ((PTEntry->PFN1 << 6) | (PTEntry->C1 << 3) | (PTEntry->D1 << 2) | (PTEntry->V1 << 1) | PTEntry->G);
                }}); // Need to hook up to TLB

                0x02: tlbwi({{
                                //Create PTE
                                MipsISA::PTE NewEntry;
                                //Write PTE
                                NewEntry.Mask = (Addr)(PageMask >> 11);
                                NewEntry.VPN = (Addr)(EntryHi >> 11);
                                /*  PageGrain _ ESP                    Config3 _ SP */
                                if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) {
                                  NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes
                                  NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled
                                }
                                NewEntry.asid = (uint8_t)(EntryHi & 0xFF);

                                NewEntry.PFN0 = (Addr)(EntryLo0 >> 6);
                                NewEntry.PFN1 = (Addr)(EntryLo1 >> 6);
                                NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
                                NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
                                NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
                                NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
                                NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
                                NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
                                NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
                                /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */
                                /* Addr Shift Amount for 1KB or larger pages */
                                //	    warn("PTE->Mask: %x\n",pte->Mask);
                                if((NewEntry.Mask & 0xFFFF) == 3){
                                  NewEntry.AddrShiftAmount = 12;
                                } else if((NewEntry.Mask & 0xFFFF) == 0x0000){
                                  NewEntry.AddrShiftAmount = 10;
                                } else if((NewEntry.Mask & 0xFFFC) == 0x000C){
                                  NewEntry.AddrShiftAmount = 14;
                                } else if((NewEntry.Mask & 0xFFF0) == 0x0030){
                                  NewEntry.AddrShiftAmount = 16;
                                } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){
                                  NewEntry.AddrShiftAmount = 18;
                                } else if((NewEntry.Mask & 0xFF00) == 0x0300){
                                  NewEntry.AddrShiftAmount = 20;
                                } else if((NewEntry.Mask & 0xFC00) == 0x0C00){
                                  NewEntry.AddrShiftAmount = 22;
                                } else if((NewEntry.Mask & 0xF000) == 0x3000){
                                  NewEntry.AddrShiftAmount = 24;
                                } else if((NewEntry.Mask & 0xC000) == 0xC000){
                                  NewEntry.AddrShiftAmount = 26;
                                } else if((NewEntry.Mask & 0x30000) == 0x30000){
                                  NewEntry.AddrShiftAmount = 28;
                                } else {
                                  fatal("Invalid Mask Pattern Detected!\n");
                                }
                                NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1);

                                MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr();
                                MiscReg c3=xc->readMiscReg(MipsISA::Config3);
                                MiscReg pg=xc->readMiscReg(MipsISA::PageGrain);
                                int SP=0;
                                if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){
                                  SP=1;
                                }
                                Ptr->insertAt(NewEntry,Index & 0x7FFFFFFF,SP);
              }});
                0x06: tlbwr({{
                                //Create PTE
                                MipsISA::PTE NewEntry;
                                //Write PTE
                                NewEntry.Mask = (Addr)(PageMask >> 11);
                                NewEntry.VPN = (Addr)(EntryHi >> 11);
                                /*  PageGrain _ ESP                    Config3 _ SP */
                                if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) {
                                  NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes
                                  NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled
                                }
                                NewEntry.asid = (uint8_t)(EntryHi & 0xFF);

                                NewEntry.PFN0 = (Addr)(EntryLo0 >> 6);
                                NewEntry.PFN1 = (Addr)(EntryLo1 >> 6);
                                NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
                                NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
                                NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
                                NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
                                NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
                                NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);